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公开(公告)号：US09521349B2
公开(公告)日：2016-12-13
申请号：US14727869
申请日：2015-06-02
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Jay Endsley , Michael Guidash
CPC classification number: H04N5/378 , H04N5/3454 , H04N5/3698 , H04N5/376
Abstract: Pixels within an image sensor pixel array are sampled by corresponding conditional read circuitry. A zero pixel value is outputted for each pixel associated with a sample less than a conversion threshold, and a saturated pixel value is outputted for each pixel associated with a sample greater than or equal to a saturation threshold. Samples greater than or equal to the conversion threshold and less than the saturation threshold are converted by an ADC, and a converted pixel value is output for each associated above threshold pixel. The ADC (along with any corresponding amplifiers) are powered on for a variable period depending on the number of pixels needing conversion during the conversion of such samples during a read period, and are powered off for the remainder of the read period.
Abstract translation: 图像传感器像素阵列内的像素通过相应的条件读取电路进行采样。 对于与小于转换阈值的样本相关联的每个像素输出零像素值，并且对于与大于或等于饱和阈值的样本相关联的每个像素输出饱和像素值。 通过ADC转换大于或等于转换阈值且小于饱和阈值的样本，并为每个相关联的上述阈值像素输出转换的像素值。 取决于在读取周期期间这样的样本的转换期间需要转换的像素的数量，ADC（以及任何相应的放大器）以及可变周期被加电，并且在读取周期的其余部分中断电。
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公开(公告)号：US20160307609A1
公开(公告)日：2016-10-20
申请号：US15138424
申请日：2016-04-26
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
CPC classification number: G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US09438826B2
公开(公告)日：2016-09-06
申请号：US14135014
申请日：2013-12-19
Applicant: Rambus Inc.
Inventor： Song Xue , Thomas Vogelsang
IPC: H01L27/146 , H04N5/335 , H04N5/347 , H04N5/357 , H04N5/3745 , H04N5/378
CPC classification number: H04N5/335 , H04N5/347 , H04N5/3575 , H04N5/37457 , H04N5/378
Abstract: An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable.
Abstract translation: 一种图像传感器，其包括具有条件复位电路的图像像素的像素阵列。 可以通过行选择和列复位信号的组合来复位像素，其实现复位功能，同时最小化额外信号线的数量。 像素还可以包括固定的光电二极管。 使用钉扎光电二极管的方式降低了噪声，并允许像素电路的量化是可编程的。
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公开(公告)号：US20160231962A1
公开(公告)日：2016-08-11
申请号：US15022176
申请日：2014-09-23
Applicant: RAMBUS INC.
Inventor： Frederick A. Ware , Thomas Vogelsang
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/0638 , G06F3/0673 , G06F11/1076 , G11C7/1006 , G11C7/1009 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2029/0411 , G11C2207/107
Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
Abstract translation: 存储器组件包括存储器组和用于接收读取 - 修改 - 写入命令的命令接口，其具有指示存储器组中的位置的相关联的读取地址，以及从读取的指示的存储器组中的位置访问读取数据 从接收到读 - 修改 - 写入命令的时间开始，或者与多个读 - 修改 - 写入命令重叠，可调节延迟时间之后的地址。 存储器组件还包括用于接收与读取 - 修改 - 写入命令相关联的写入数据的数据接口和用于将接收到的写入数据与读取的数据合并以形成合并数据的纠错电路，并将合并的数据写入到 由读取地址指示的存储体。
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公开(公告)号：US09344635B2
公开(公告)日：2016-05-17
申请号：US14355799
申请日：2012-11-08
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , David Geoffrey Stork , John Eric Linstadt , James E. Harris
CPC classification number: H04N5/235 , H04N1/00769 , H04N5/2355 , H04N5/3355 , H04N5/3535 , H04N5/355 , H04N5/35536 , H04N5/3745
Abstract: Pixel circuits in an image sensor are sampled repetitively during an image frame period. At each sampling, a signal indicative of the photocharge integrated by a pixel circuit since last reset is compared to a threshold. If the integrated photocharge signal has not reached the threshold, the pixel circuit is permitted to continue integrating photocharge. If the integrated photocharge signal has reached the threshold, the pixel circuit is reset to remove integrated photocharge and photocharge integration for that pixel circuit is restarted. A corresponding pixel circuit value is recorded for the reset pixel circuit.
Abstract translation: 图像传感器中的像素电路在图像帧周期期间重复采样。 在每次采样时，将与上一次复位后的像素电路集成的光电荷的信号与阈值进行比较。 如果集成光电荷信号尚未达到阈值，则允许像素电路继续积分光电荷。 如果积分的光电荷信号已经达到阈值，则像素电路被复位以去除集成的光电荷并且该像素电路的光电荷积分被重新启动。 记录复位像素电路的对应像素电路值。
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Patent Agency Ranking
公开(公告)号：US20160005455A1
公开(公告)日：2016-01-07
申请号：US14833028
申请日：2015-08-21
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Brent Haukness , Stephen Charles Bowyer
IPC: G11C11/4096 , G11C11/4091 , G11C11/408
CPC classification number: G11C11/4096 , G06F12/00 , G06F13/1694 , G11C11/4087 , G11C11/4091 , Y02D10/14
Abstract: Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.
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公开(公告)号：US20150373290A1
公开(公告)日：2015-12-24
申请号：US14727869
申请日：2015-06-02
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Jay Endsley , Michael Guidash
CPC classification number: H04N5/378 , H04N5/3454 , H04N5/3698 , H04N5/376
Abstract: Pixels within an image sensor pixel array are sampled by corresponding conditional read circuitry. A zero pixel value is outputted for each pixel associated with a sample less than a conversion threshold, and a saturated pixel value is outputted for each pixel associated with a sample greater than or equal to a saturation threshold. Samples greater than or equal to the conversion threshold and less than the saturation threshold are converted by an ADC, and a converted pixel value is output for each associated above threshold pixel. The ADC (along with any corresponding amplifiers) are powered on for a variable period depending on the number of pixels needing conversion during the conversion of such samples during a read period, and are powered off for the remainder of the read period.
Abstract translation: 图像传感器像素阵列内的像素通过相应的条件读取电路进行采样。 对于与小于转换阈值的样本相关联的每个像素输出零像素值，并且对于与大于或等于饱和阈值的样本相关联的每个像素输出饱和像素值。 通过ADC转换大于或等于转换阈值且小于饱和阈值的样本，并为每个相关联的上述阈值像素输出转换的像素值。 取决于在读取周期期间这样的样本的转换期间需要转换的像素的数量，ADC（以及任何相应的放大器）以及可变周期被加电，并且在读取周期的其余部分中断电。
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公开(公告)号：US20150070544A1
公开(公告)日：2015-03-12
申请号：US14482065
申请日：2014-09-10
Applicant: Rambus Inc.
Inventor： Craig M. Smith , Michael Guidash , Jay Endsley , Thomas Vogelsang , James E. Harris
IPC: H04N5/378
CPC classification number: H04N5/3559 , H01L27/14621 , H01L27/14627 , H01L27/14641 , H01L27/14643 , H01L27/14645 , H04N5/347 , H04N5/355 , H04N5/3741 , H04N5/37455 , H04N5/378
Abstract: In a pixel array within an integrated-circuit image sensor, each of a plurality of pixels is evaluated to determine whether charge integrated within the pixel in response to incident light exceeds a first threshold. N-bit digital samples corresponding to the charge integrated within at least a subset of the plurality of pixels are generated, and then applied to a lookup table to retrieve respective M-bit digital values (M being less than N), wherein a stepwise range of charge integration levels represented by possible states of the M-bit digital values extends upward from a starting charge integration level that is determined based on the first threshold.
Abstract translation: 在集成电路图像传感器内的像素阵列中，评估多个像素中的每一个以确定响应于入射光在像素内积分的电荷是否超过第一阈值。 产生与集成在多个像素的至少一个子集中的电荷相对应的N位数字样本，然后将其应用于查找表以检索相应的M位数字值（M小于N），其中步长范围 由M位数字值的可能状态表示的电荷积分电平从基于第一阈值确定的起始电荷积分电平向上延伸。
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公开(公告)号：US20140175264A1
公开(公告)日：2014-06-26
申请号：US14135014
申请日：2013-12-19
Applicant: Rambus Inc.
Inventor： Song Xue , Thomas Vogelsang
IPC: H01L27/146
CPC classification number: H04N5/335 , H04N5/347 , H04N5/3575 , H04N5/37457 , H04N5/378
Abstract: An image sensor that includes a pixel array with image pixels with conditional reset circuitry. The pixels can be reset by a combination of row select and column reset signals, which implements the reset function while minimizing the number of extra signal lines. The pixels may also include pinned photodiodes. The manner in which the pinned photodiodes are used reduces noise and allows the quantization of the pixel circuits to be programmable.
Abstract translation: 一种图像传感器，其包括具有条件复位电路的图像像素的像素阵列。 可以通过行选择和列复位信号的组合来复位像素，其实现复位功能，同时最小化额外信号线的数量。 像素还可以包括固定的光电二极管。 使用钉扎光电二极管的方式降低了噪声，并允许像素电路的量化是可编程的。
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公开(公告)号：US20250028467A1
公开(公告)日：2025-01-23
申请号：US18794915
申请日：2024-08-05
Applicant: Rambus Inc.
Inventor： Michael Raymond MILLER , Steven C. Woo , Thomas Vogelsang
Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.
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