公开(公告)号：US20070090436A1

公开(公告)日：2007-04-26

申请号：US11565633

申请日：2006-12-01

Applicant: Chao-Hsi Chung

Inventor： Chao-Hsi Chung

IPC: H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  H01L29/945

Abstract: A deep trench capacitor disposed in a deep trench in a substrate is provided. The deep trench capacitor includes a bottom electrode disposed in the substrate surrounding a bottom of the deep trench; a first conductive layer disposed in the deep trench; a capacitor dielectric layer disposed between a lower surface of the deep trench and the first conductive layer; a second conductive layer disposed in the deep trench and above the first conductive layer; a collar oxide layer disposed between an upper surface of the deep trench and the second conductive layer; a third conductive layer disposed in the deep trench and above the second conductive layer; an isolation structure disposed in parts of the third conductive layer, the second conductive layer and the substrate; and an isolation layer disposed below the isolation structure and in parts of the second conductive layer and the substrate.

Abstract translation: 提供了设置在衬底中的深沟槽中的深沟槽电容器。 深沟槽电容器包括设置在衬底中的底部电极，围绕深沟槽的底部; 布置在所述深沟槽中的第一导电层; 设置在所述深沟槽的下表面和所述第一导电层之间的电容器电介质层; 设置在所述深沟槽中并位于所述第一导电层上方的第二导电层; 设置在所述深沟槽的上表面和所述第二导电层之间的环状氧化物层; 设置在所述深沟槽中并位于所述第二导电层上方的第三导电层; 设置在所述第三导电层，所述第二导电层和所述基板的一部分中的隔离结构; 以及隔离层，其设置在隔离结构的下方以及第二导电层和基板的一部分中。

公开(公告)号：US07190019B2

公开(公告)日：2007-03-13

申请号：US11013593

申请日：2004-12-14

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/787 ,  H01L29/788 ,  H01L29/336

CPC classification number: H01L27/11526 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/11529

Abstract: A widened contact area (170X) of a conductive feature (170) is formed by means of self-alignment between an edge (170E2) of the conductive feature and an edge (140E) of another feature (140). The other feature (“first feature”) is formed from a first layer, and the conductive feature is formed from a second layer overlying the first layer. The edge (170E2) of the conductive feature is shaped to provide a widened contact area. This shaping is achieved in a self-aligned manner by shaping the corresponding edge (140E) of the first feature.

Abstract translation: 通过在导电特征的边缘（170E2）与另一特征（140）的边缘（140E）之间的自对准，形成导电特征（170）的加宽的接触区域（170×）。 另一特征（“第一特征”）由第一层形成，并且导电特征由覆盖第一层的第二层形成。 导电特征的边缘（170E 2）成形为提供加宽的接触面积。 通过使第一特征的对应边缘（140E）成形，以自对准的方式实现该成形。

公开(公告)号：US20070004130A1

公开(公告)日：2007-01-04

申请号：US11463896

申请日：2006-08-11

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242 ,  H01L29/94

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US20060263701A1

公开(公告)日：2006-11-23

申请号：US11181942

申请日：2005-07-15

Applicant: Yee Lai

Inventor： Yee Lai

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/30

Abstract: The present method for preparing a Levenson phase shifting mask first forms a metal layer on a substrate, and an etching process is performed to form a plurality of openings in the metal layer. A spin-coating process is performed to form a polymer layer on the substrate, an electron beam is then used to irradiate on a predetermined region of the polymer layer, and the polymer layer outside the predetermined region is removed. The polymer layer may consist of hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ) or hybrid organic siloxane polymer (HOSP), and an alkaline solution, alcohol solution or propyl acetate can be used to remove the polymer layer outside the predetermined region. The alkaline solution is selected from the group consisting of sodium hydroxide (NaOH), potassium hydroxide (KOH) and tetramethylamomnium hydroxide (TMAH).

Abstract translation: 本发明的Levenson相移掩模的制造方法首先在基板上形成金属层，并进行蚀刻处理，以在金属层中形成多个开口。 进行旋涂工艺以在基板上形成聚合物层，然后使用电子束照射聚合物层的预定区域，并且除去预定区域外的聚合物层。 聚合物层可由氢倍半硅氧烷（HSQ），甲基倍半硅氧烷（MSQ）或杂化有机硅氧烷聚合物（HOSP）组成，碱性溶液，乙醇溶液或乙酸丙酯可用于除去预定区域外的聚合物层。 碱性溶液选自氢氧化钠（NaOH），氢氧化钾（KOH）和四甲基氢氧化铵（TMAH）。

公开(公告)号：US20060245293A1

公开(公告)日：2006-11-02

申请号：US11456891

申请日：2006-07-12

Applicant: Jon Faue

Inventor： Jon Faue

IPC: G11C8/00

CPC classification number: G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block within the clock generator detects when a read or write is active and initiates a YCLK signal on the next falling edge of the internal clock. Two separate mechanisms are used for determining when to terminate the YCLK. One mechanism is a timer path and the other is a path determined by DDR1 and DDR2 control signals. The timer path is strictly time based and is the same for DDR1 and DDR2 parts or modes of operation. The other signal path is different for DDR1 and DDR2 operating modes. A DDR1 control signal turns off YCLK at the next rising edge of the internal clock, and a DDR2 control signal turns off YCLK at the next falling edge of the internal clock.

Abstract translation: 提供与DDR1和DDR2应用兼容的时钟发生器。 即使主芯片时钟始终运行，内部YCLK信号仅在集成电路存储器上发生有效读取或写入时导通。 时钟发生器内的一个电路块检测读或写何时有效，并在内部时钟的下一个下降沿启动YCLK信号。 使用两个单独的机制来确定何时终止YCLK。 一种机制是定时器路径，另一种是由DDR1和DDR2控制信号确定的路径。 定时器路径是基于时间的，对于DDR1和DDR2部件或操作模式是相同的。 DDR1和DDR2操作模式的其他信号路径不同。 DDR1控制信号在内部时钟的下一个上升沿关闭YCLK，DDR2控制信号在内部时钟的下一个下降沿关闭YCLK。

公开(公告)号：US07126854B2

公开(公告)日：2006-10-24

申请号：US10780031

申请日：2004-02-17

Applicant: Jongmin Park

Inventor： Jongmin Park

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: The sequence in which the voltages (VSL, VDL, VSG, and VCL) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor (20) start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (VSL) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.

Abstract translation: 电压（V SUB），V SUB，V SUB，V SUB和V CL CL的序列应用于 在编程操作期间，浮置栅极场效应晶体管（20）的源/漏区（S和D），选择栅（SG）和（如果存在）控制栅（CG）开始改变值被控制为 以避免在晶体管保持处于擦除状态时避免将晶体管的可编程阈值电压调整为编程值，即不进入编程状态。 在一个源极/漏极区域（S）处的电压（V SUB SL）从标称值变化到编程值的情况下，该序列使得选择栅极处的电压（SG）开始从 在另一个源极/漏极区域（D）处的电压开始从标称值改变到编程禁止值之后的编程使能值的标称值。

公开(公告)号：US20060228852A1

公开(公告)日：2006-10-12

申请号：US11104213

申请日：2005-04-12

Applicant: Jung-Wu Chien

Inventor： Jung-Wu Chien

IPC: H01L21/8244 ,  H01L21/4763

CPC classification number: H01L21/76877 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76897 ,  H01L27/10885 ,  H01L27/10894

Abstract: A method of forming cell bitline contact plugs is disclosed in the present invention. After providing a semiconductor substrate with a first region and a second region, cell bitline contacts are formed at the first region. After forming bitline pattern openings at the second region, poly spacers are formed on sidewalls of the cell bitline contacts and the bitline pattern openings. A substrate contact and a gate contact are then formed within the openings at the second region. After forming a trench around each of the substrate contact and the gate contact by performing an etching process, cell-bitline contact plugs, a substrate contact plug, and a gate contact plug are formed.

公开(公告)号：US07119390B2

公开(公告)日：2006-10-10

申请号：US10711939

申请日：2004-10-14

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10841 ,  H01L27/0207 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 所述电容器包括位于所述支柱侧壁下部的第一板，在所述第一板的周边处的作为上部电极的第二板，在所述第二板的外围的第三板与所述第一板电连接以形成 下电极和将第二板与第一和第三板分离的电介质层。 还描述了基于DRAM单元的DRAM阵列和用于制造DRAM阵列的方法。

公开(公告)号：US20060205144A1

公开(公告)日：2006-09-14

申请号：US11114152

申请日：2005-04-26

Applicant: Hui Li ,  Jung Chien ,  Chao Chung ,  Ming Lin

Inventor： Hui Li ,  Jung Chien ,  Chao Chung ,  Ming Lin

IPC: H01L21/8242

CPC classification number: H01L29/66181 ,  H01L27/10861

Abstract: The present invention discloses a trench capacitor formed in a trench in a semiconductor substrate. The trench capacitor comprises a bottom electrode positioned on a lower outer surface of the trench, a dielectric layer positioned on an inner surface of the bottom electrode, a top electrode positioned on the dielectric layer, a collar oxide layer positioned on an upper inner surface of the trench, a buried conductive strap positioned on the top electrode, and an interface layer made of silicon nitride positioned at the side of the buried conductive strap. The bottom electrode, the dielectric layer and the top electrode form a capacitive structure. The collar oxide layer includes a first block and a second block, and the height of the first block is larger than the height of the second block. The interface layer is positioned on a portion of the inner surface of the trench above the second block.

Abstract translation: 本发明公开了一种在半导体衬底的沟槽中形成的沟槽电容器。 所述沟槽电容器包括位于所述沟槽的下外表面上的底电极，位于所述底电极的内表面上的电介质层，位于所述电介质层上的顶电极，位于所述电介质层的上内表面上的环状氧化物层 沟槽，位于顶部电极上的埋入导电带，以及位于掩埋导电带侧面的由氮化硅制成的界面层。 底部电极，电介质层和顶部电极形成电容结构。 环状氧化物层包括第一块和第二块，并且第一块的高度大于第二块的高度。 界面层位于第二块上方的沟槽的内表面的一部分上。

公开(公告)号：US07101757B2

公开(公告)日：2006-09-05

申请号：US10632155

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  G11C16/0458 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

Abstract: In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current.

Abstract translation: 在非易失性存储单元（110）中，选择栅极晶体管形成为埋入沟道晶体管以增加晶体管电流。