公开(公告)号：US11621277B2

公开(公告)日：2023-04-04

申请号：US17098743

申请日：2020-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Zhixin Cui ,  Senaka Kanakamedala ,  Yao-Sheng Lee ,  Chih-Yu Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

公开(公告)号：US20230102668A1

公开(公告)日：2023-03-30

申请号：US17487665

申请日：2021-09-28

Applicant: SanDisk Technologies LLC.

Inventor： Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. The memory apparatus also includes a control means coupled to the plurality of word lines and the strings. The control means is configured to identify the at least one edge word line. The control means is also configured to periodically apply a program voltage to the at least one edge word line to reprogram the memory cells associated with the at least one edge word line without erasing the memory cells associated with the at least one edge word line.

公开(公告)号：US20230101414A1

公开(公告)日：2023-03-30

申请号：US17552143

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Martin Hassner ,  Michael Nicolas Albert Tran ,  Ward Parkinson ,  Michael Grobis ,  Nathan Franklin ,  Raj Ramanujan

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C29/12

Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).

公开(公告)号：US20230099107A1

公开(公告)日：2023-03-30

申请号：US17485949

申请日：2021-09-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Peng ZHANG

IPC: H01L27/11551 ,  H01L27/11578 ,  H01L27/11529 ,  H01L27/11573

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

公开(公告)号：US20230095127A1

公开(公告)日：2023-03-30

申请号：US17731971

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： YenLung Li ,  Siddarth Naga Murty Bassa ,  Chen Chen ,  Hua-Ling Cynthia Hsu

IPC: G06F3/06

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US11615839B2

公开(公告)日：2023-03-28

申请号：US17368727

申请日：2021-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11565 ,  H01L25/065 ,  H01L27/11582

Abstract: In a three dimensional non-volatile memory structure that etches part of the top of the memory structure (including a portion of the select gates), data is stored on a majority (or all but one) of the word lines as x bits per memory cell while data is stored on a top edge word line that is closest to the etching with variable bits per memory cell. In one example embodiment that implements vertical NAND strings, memory cells connected to the top edge word line and that are on NAND strings adjacent the etching store data as n bits per memory cell and memory cells connected to the top edge word line and that are on NAND strings not adjacent the etching store data as m bits per memory cell, where m>x>n.

公开(公告)号：US11610625B2

公开(公告)日：2023-03-21

申请号：US17349040

申请日：2021-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroki Yabe

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/4094

Abstract: A flash memory die includes (i) a first subset of planes including blocks of flash memory cells connected to a first number of word line layers and a plurality of bit lines having a first length, (ii) a second subset of planes including blocks of flash memory cells connected to a second number of word line layers less than the first number of word line layers and a plurality of bit lines having a second length shorter than the first length, (iii) first peripheral circuitry implemented underneath the first subset of planes and including first sense amplifier circuitry and first peripheral control circuitry connected to the first subset of planes, and second peripheral control circuitry connected to the second subset of planes, and (iv) second peripheral circuitry implemented underneath the second subset of planes and including second sense amplifier circuitry connected to the second subset of planes.

公开(公告)号：US20230085405A1

公开(公告)日：2023-03-16

申请号：US17731961

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

公开(公告)号：US20230078456A1

公开(公告)日：2023-03-16

申请号：US17473183

申请日：2021-09-13

Applicant: SanDisk Technologies LLC

Inventor： Ke Zhang ,  Liang Li

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/12 ,  G11C16/08

Abstract: A memory device including an array of memory cells arranged in a plurality of word lines is provided. A control circuitry is configured to program the memory cells of a selected word line to a plurality of leading data states in a plurality of programming loops that include programming and verify pulses. The control circuitry is also configured to count a total number of programming loops during programming of the selected word line. The control circuitry is also configured to program at least one memory cell of the selected word line to a last data state in at least one last data state programming loop. In response to both the total number of programming loops being less than a first predetermined threshold and the number of last data state programming loops being equal to a second predetermined threshold, the control circuitry automatically skips verify in a final programming loop.

公开(公告)号：US11598005B2

公开(公告)日：2023-03-07

申请号：US16868787

申请日：2020-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shoichi Murakami ,  Shigeru Nakatsuka ,  Syo Fukata ,  Yusuke Osawa ,  Shigehiro Fujino ,  Masaaki Higashitani

IPC: H01L21/683 ,  C23C16/458 ,  H01L21/02 ,  H01L21/687 ,  H01J37/32 ,  H01L21/033 ,  C23C16/50 ,  C23C16/455

Abstract: A deposition chamber includes a vacuum enclosure, an electrostatic chuck having a flat top surface located within a vacuum enclosure, a lift-and-rotation unit extending through or laterally surrounding the electrostatic chuck at a position that is laterally offset from a vertical axis passing through a geometrical center of the electrostatic chuck, a gas supply manifold configured to provide influx of gas into the vacuum enclosure, and a pumping port connected to the vacuum enclosure.