公开(公告)号：US20240090233A1

公开(公告)日：2024-03-14

申请号：US18515289

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Wang ,  Yi-An Shih ,  Huan-Chi Ma

IPC: H10B61/00

CPC classification number: H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

公开(公告)号：US20240085780A1

公开(公告)日：2024-03-14

申请号：US17965730

申请日：2022-10-13

Applicant: United Microelectronics Corp.

Inventor： Chia-Chen Sun ,  En-Chiuan Liou ,  Song-Yi Lin

IPC: G03F1/76 ,  G03F1/36

CPC classification number: G03F1/76 ,  G03F1/36

Abstract: A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.

公开(公告)号：US11929431B2

公开(公告)日：2024-03-12

申请号：US18138145

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

公开(公告)号：US11923435B2

公开(公告)日：2024-03-05

申请号：US17723438

申请日：2022-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Han Wu ,  Kai-Kuen Chang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L29/66674 ,  H01L29/7801

Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first drift region, a gate structure, a first sub gate structure, a first spacer structure, a second spacer structure, and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub gate structure. The first sub gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub gate structure. At least a part of the first insulation structure is located between the first spacer structure and the second spacer structure. The first insulation structure is directly connected with the first drift region located between the first spacer structure and the second spacer structure.

公开(公告)号：US11923373B2

公开(公告)日：2024-03-05

申请号：US17502026

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo Tao ,  Li Wang ,  Ching-Yang Wen ,  Purakh Raj Verma ,  Zhibiao Zhou ,  Dong Yin ,  Gang Ren ,  Jian Xie

IPC: H01L27/12 ,  G11C17/16 ,  H01L23/525 ,  H10B20/20 ,  H10B20/25

CPC classification number: H01L27/1207 ,  G11C17/16 ,  G11C17/165 ,  H01L23/5252 ,  H10B20/20 ,  H10B20/25

Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

公开(公告)号：US20240074209A1

公开(公告)日：2024-02-29

申请号：US18500994

申请日：2023-11-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/5226 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.

公开(公告)号：US20240072153A1

公开(公告)日：2024-02-29

申请号：US18506101

申请日：2023-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66431 ,  H01L29/7786

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

公开(公告)号：US20240072129A1

公开(公告)日：2024-02-29

申请号：US18504165

申请日：2023-11-08

Applicant: United Microelectronics Corp.

Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/40114 ,  H01L21/76224 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/788 ,  H01L21/31051

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

公开(公告)号：US20240072126A1

公开(公告)日：2024-02-29

申请号：US17952298

申请日：2022-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, performing an ion implantation process to form a hole injection buffer layer (HIBL) on the p-type semiconductor layer, and then forming a gate electrode on the HIBL.

公开(公告)号：US20240071818A1

公开(公告)日：2024-02-29

申请号：US17950120

申请日：2022-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Wei Chi ,  Te-Chang Hsu ,  Yao-Jhan Wang ,  Meng-Yun Wu ,  Chun-Jen Huang

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/76829 ,  H01L21/02041 ,  H01L21/02293 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/66795

Abstract: A semiconductor device and method of fabricating the same include a substrate, a first epitaxial layer, a first protection layer, and a contact etching stop layer. The substrate includes a PMOS transistor region, and the first epitaxial layer is disposed on the substrate, within the PMOS transistor region. The first protection layer is disposed on the first epitaxial layer, covering surfaces of the first epitaxial layer. The contact etching stop layer is disposed on the first protection layer and the substrate, wherein a portion of the first protection layer is exposed from the contact etching stop layer.