公开(公告)号：US20230299668A1

公开(公告)日：2023-09-21

申请号：US18323304

申请日：2023-05-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

CPC classification number: H02M3/07 ,  G05F3/10 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/17 ,  H01L29/66181 ,  H01L2224/02379

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US11735567B2

公开(公告)日：2023-08-22

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L21/78 ,  H01L22/32 ,  H01L23/481 ,  H01L23/60 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/30205

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20230245988A1

公开(公告)日：2023-08-03

申请号：US18058006

申请日：2022-11-22

Applicant: Apple Inc.

Inventor： Kwan-Yu Lai ,  Kunzhong Hu ,  Jun Zhai ,  Young Doo Jeon

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L24/73 ,  H01L24/13 ,  H01L24/20 ,  H01L24/19 ,  H01L24/14 ,  H01L2224/73101 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/19 ,  H01L2224/11002 ,  H01L2224/11916 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/1184 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13075 ,  H01L2224/13541 ,  H01L2224/13552 ,  H01L2224/13575 ,  H01L2924/35121

Abstract: Die reconstitution methods and dies with reconstituted contact bumps are described. In an embodiment, a die reconstitution method includes reconstituting a plurality of dies including first contact bumps of a first type, partially removing the first contact bumps, and forming second contact bumps of a second type on top of the partially removed first contact bumps, where the second type is different than the first type.

公开(公告)号：US20230115986A1

公开(公告)日：2023-04-13

申请号：US18046134

申请日：2022-10-12

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Chih-Ming Chung ,  Jun Zhai ,  Yifan Kao ,  Young Doo Jeon ,  Taegui Kim

IPC: H01L23/00

Abstract: Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

公开(公告)号：US11561144B1

公开(公告)日：2023-01-24

申请号：US16262724

申请日：2019-01-30

Applicant: Apple Inc.

Inventor： Caleb C. Han ,  Brad G. Boozer ,  Mark G. Walsh ,  William S. Lee ,  Tongbi T. Jiang ,  Jun Zhai ,  Yun X. Ma ,  James G. Horiuchi ,  David MacNeil ,  Ashwin Balasubramanian ,  Wei Chen ,  Jie-Hua Zhao

IPC: G04G21/02 ,  G01L7/08 ,  G01C5/06 ,  G04G17/02 ,  G04B47/06 ,  G04G21/08

Abstract: An electronic device, such as a smart watch, incorporating a fluid-based pressure-sensing device is disclosed. The fluid-based pressure-sensing device includes an enclosure, a pressure sensor, a diaphragm and a sensing medium. The enclosure includes an opening and the pressure sensor is disposed inside the enclosure. The diaphragm hermetically seals the opening, and the sensing medium transfers a pressure exerted on the diaphragm to the pressure sensor. The sensing medium can be liquid oil filling a space of the enclosure, and the diaphragm is a polymer material. The pressure-sensing device may sense an environmental pressure, which may be used by the electronic device to modify its operations, change information that is displayed, and so on.

公开(公告)号：US20220285273A1

公开(公告)日：2022-09-08

申请号：US17699563

申请日：2022-03-21

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：US20220014095A1

公开(公告)日：2022-01-13

申请号：US17383983

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US11217563B2

公开(公告)日：2022-01-04

申请号：US16869468

申请日：2020-05-07

Applicant: Apple Inc.

Inventor： Jun Zhai

IPC: H01L25/065

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

公开(公告)号：US20210305227A1

公开(公告)日：2021-09-30

申请号：US17013279

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20210242170A1

公开(公告)日：2021-08-05

申请号：US16783132

申请日：2020-02-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Zhitao Cao ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H05K1/11 ,  H05K1/18

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (TO) density and routing quality for signals, while keeping power delivery feasible.