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    VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS
    162.
    发明申请
    VARIABLE RESISTANCE MEMORY WITH LATTICE ARRAY USING ENCLOSING TRANSISTORS 审中-公开

    公开(公告)号：US20190057739A1

    公开(公告)日：2019-02-21

    申请号：US16153143

    申请日：2018-10-05

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/063 ,  G11C11/4097 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

    Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

    Methods for forming narrow vertical pillars and integrated circuit devices having the same
    164.
    发明授权
    Methods for forming narrow vertical pillars and integrated circuit devices having the same 有权

    公开(公告)号：US10164178B2

    公开(公告)日：2018-12-25

    申请号：US15462618

    申请日：2017-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal Parekh

    IPC: H01L27/24 ,  H01L45/00

    Abstract: In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

    Unidirectional spin torque transfer magnetic memory cell structure
    165.
    发明授权
    Unidirectional spin torque transfer magnetic memory cell structure 有权

    公开(公告)号：US10127962B2

    公开(公告)日：2018-11-13

    申请号：US15413037

    申请日：2017-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: G11C11/16 ,  H01L43/02

    Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

    Unidirectional spin torque transfer magnetic memory cell structure
    169.
    发明授权
    Unidirectional spin torque transfer magnetic memory cell structure 有权
    单向自旋转矩传递磁存储单元结构

    公开(公告)号：US09589618B2

    公开(公告)日：2017-03-07

    申请号：US14553758

    申请日：2014-11-25

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Gurtej Sandhu

    IPC: G11C11/16 ,  H01L43/02

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

    Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

    Abstract translation: 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

    Arrays of memory cells and methods of forming an array of memory cells
    170.
    发明授权
    Arrays of memory cells and methods of forming an array of memory cells 有权
    存储单元阵列和形成存储单元阵列的方法

    公开(公告)号：US09553262B2

    公开(公告)日：2017-01-24

    申请号：US13761570

    申请日：2013-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Kunal R. Parekh

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

    Abstract translation: 存储单元阵列包括具有导电掺杂半导体材料的掩埋访问线。 支柱向外延伸并沿着掩埋的进入管线间隔开。 支柱分别包括一个记忆单元。 外部接入线在柱子和埋入式接入线路的正上方。 外部接入线路比埋入式接入线路的导电性高。 多个导电通孔沿着并且电耦合埋入和外部接入线路中的各个对间隔开。 多个支柱在沿对之间的通孔的紧邻之间。 导电金属材料直接抵靠埋入式接入线路的顶部，并沿独立的埋入式接入线路在支柱之间延伸。 公开了包括方法的其它实施例。

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