公开(公告)号：US5625603A

公开(公告)日：1997-04-29

申请号：US477244

申请日：1995-06-07

申请人： David C. McClure ,  Thomas A. Teel

发明人： David C. McClure ,  Thomas A. Teel

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： An integrated circuit with an integer odd number C of electrical contacts, wherein each of the electrical contacts is for communicating a data value. The integrated circuit also includes four memory arrays for storing data. The first and third memory arrays are operable to simultaneously output an integer even number E of data values. The second and fourth memory arrays are operable to simultaneously output an integer odd number D of data values. The integrated circuit further includes circuitry for selectively coupling the first, second, third, and fourth memory arrays to the electrical contacts, wherein the circuitry for selectively coupling is operable to couple the first and fourth memory arrays to the electrical contacts in a first state so that the first memory array outputs E data values and the fourth memory array outputs D data values in the first state. The circuitry for selectively coupling is also operable to couple the second and third memory arrays to the electrical contacts in a second state so that the second memory array outputs D data values and the third memory array outputs E data values in the second state.

摘要翻译： 一种具有整数奇数C的电触点的集成电路，其中每个电触点用于传送数据值。 集成电路还包括用于存储数据的四个存储器阵列。 第一和第三存储器阵列可操作以同时输出数据值的整数偶数E。 第二和第四存储器阵列可操作以同时输出数据值的整数奇数D。 集成电路还包括用于将第一，第二，第三和第四存储器阵列选择性地耦合到电触点的电路，其中用于选择性耦合的电路可操作以在第一状态下将第一和第四存储器阵列耦合到电触点 第一存储器阵列输出E数据值，第四存储器阵列输出处于第一状态的D数据值。 用于选择性耦合的电路还可操作以在第二状态下将第二和第三存储器阵列耦合到电触点，使得第二存储器阵列输出D数据值，而第三存储器阵列在第二状态下输出E数据值。

公开(公告)号：US5598122A

公开(公告)日：1997-01-28

申请号：US359926

申请日：1994-12-20

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G05F3/26 ,  H03K19/0185 ,  G05F1/10

CPC分类号： H03K19/018521 ,  G05F3/262

摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

摘要翻译： 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5596297A

公开(公告)日：1997-01-21

申请号：US360228

申请日：1994-12-20

申请人： David C. McClure ,  Thomas A. Teel

发明人： David C. McClure ,  Thomas A. Teel

IPC分类号： G05F3/26 ,  H03K19/0185 ,  G05F1/10

CPC分类号： G05F3/262 ,  H03K19/018521

摘要： An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

摘要翻译： 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5583816A

公开(公告)日：1996-12-10

申请号：US267667

申请日：1994-06-29

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C29/34 ,  G11C11/41

摘要： According to the present invention, a block of a static memory device, or some portion thereof, is selected to be subjected to a long write test. Choosing a portion of the static memory device, such as a block, offers the advantage of limiting current switching transients as well as recovery time following the long write test. All bitlines of the selected block are written to simultaneously for a period of time; all the wordlines within the selected block are disabled during this time so that no memory cell is selected. The bitlines of the selected block are recovered in two phases so that current switching transients are limited to a reasonable value and writing to the bitlines may be staggered. Finally, the selected block is read disturbed by cycling row fast through the selected block.

摘要翻译： 根据本发明，静态存储器件或其某些部分的块被选择进行长写入测试。 选择静态存储器件（例如块）的一部分提供限制当前开关瞬变以及长写入测试后的恢复时间的优点。 所选块的所有位线被同时写入一段时间; 在此期间，所选块内的所有字线都被禁用，因此不会选择存储单元。 所选块的位线以两个阶段恢复，使得当前的开关瞬变被限制在合理的值，并且对位线的写入可能是交错的。 最后，通过所选块快速循环行来读取所选择的块。

公开(公告)号：US5579326A

公开(公告)日：1996-11-26

申请号：US189589

申请日：1994-01-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G01R31/30 ,  G06F11/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/50 ,  G11C17/00

CPC分类号： G11C29/026 ,  G01R31/30 ,  G06F11/006 ,  G11C29/02 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50012 ,  G11C11/401 ,  G11C11/41

摘要： A method and apparatus for testing and programming signal timing are disclosed which can be incorporated into an integrated circuit device utilizing on-chip timed command signals and pulses. The method of the invention enables nonpermanent testing and retesting of a device at various operational speeds during production testing. During retesting, temporary signal delays are selectively introduced into the circuit of a device which failed a previous test due to non-repairable errors. Once a device passes the production test error-free or with repairable errors, the temporary signal delays are permanently programmed into the device. Specifically, the method utilizes one or a plurality of mode control circuits and test voltage input terminals to nonpermanently select signal delays which may be identified and permanently enabled at a later time.

摘要翻译： 公开了用于测试和编程信号定时的方法和装置，其可以使用片上定时指令信号和脉冲并入集成电路装置。 本发明的方法能够在生产测试期间以各种运行速度进行设备的非永久性测试和重新测试。 在重新测试期间，由于不可修复的错误，临时信号延迟被选择性地引入到先前测试失败的设备的电路中。 一旦设备无错误地通过生产测试或具有可修复的错误，临时信号延迟将被永久地编程到设备中。 具体地，该方法利用一个或多个模式控制电路和测试电压输入端子来非永久地选择可以在稍后时间被识别并永久启用的信号延迟。

公开(公告)号：US5568084A

公开(公告)日：1996-10-22

申请号：US357664

申请日：1994-12-16

申请人： David C. McClure ,  Thomas A. Teel

发明人： David C. McClure ,  Thomas A. Teel

IPC分类号： H03K17/14 ,  G05F3/20 ,  H03F1/30 ,  H03F3/16 ,  H03F3/45 ,  H03K17/687 ,  H03K19/00 ,  H03K19/0175 ,  G05F1/10

CPC分类号： G05F3/205

摘要： A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device. The bias circuit may control the slew rate of an output driver, may control the propagation delay through a delay element, and be used to control the duration of a pulse produced by a pulse generating circuit.

摘要翻译： 公开了一种偏置电路，用于产生偏置电压超过电源电压和过程参数的变化。 偏置电路利用分压器基于电源值产生分压。 分压电流被施加到电流镜中的调制晶体管的栅极（偏置为饱和），其控制施加到在线性区域中偏置的线性负载装置的电流。 负载器件两端的电压决定偏置电压。 因此，电源电压的变化被反映在偏置电压中，使得串联晶体管的栅极 - 源极电压在电源电压的变化上是恒定的。 产生不同晶体管电流驱动特性的工艺参数的变化反映在由线性负载装置产生的偏置电压的变化中。 偏置电路可以控制输出驱动器的转换速率，可以通过延迟元件来控制传播延迟，并且用于控制由脉冲发生电路产生的脉冲的持续时间。

公开(公告)号：US5568073A

公开(公告)日：1996-10-22

申请号：US172853

申请日：1993-12-22

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C15/04 ,  G01R19/00 ,  G11C7/00

CPC分类号： G11C7/062

摘要： According to the present invention, the delay associated with a logic stage external to a sense amplifier is eliminated by absorbing the logic state into the sense amplifier circuitry. The sense amplifier inputs are swapped based on a sense enable signal which may be a derivative signal of a Data In signal. The sense amplifier may sense continuously or it may be clocked. The sense enable circuitry may be applied to various types of sense amplifiers such as dynamic, current mirror, differential, cross coupled, and level shifting sense amplifiers.

摘要翻译： 根据本发明，通过将逻辑状态吸收到读出放大器电路中来消除与读出放大器外部的逻辑级相关联的延迟。 读出放大器输入基于可以是数据输入信号的导数信号的感测使能信号进行交换。 读出放大器可以连续感测或者可以计时。 感测使能电路可以应用于各种类型的读出放大器，例如动态，电流镜，差分，交叉耦合和电平移位读出放大器。

公开(公告)号：US5548241A

公开(公告)日：1996-08-20

申请号：US360229

申请日：1994-12-20

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G05F3/24 ,  G05F1/46 ,  G05F1/56 ,  H03F3/34 ,  H03F3/343 ,  H03F3/347 ,  H03F3/45 ,  G05F1/10

CPC分类号： H03F3/45766 ,  G05F1/465 ,  H03F3/45479 ,  H03F2203/45454 ,  H03F2203/45466 ,  H03F2203/45504 ,  H03F2203/45508

摘要： An output driver circuit for an integrate circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

摘要翻译： 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5530674A

公开(公告)日：1996-06-25

申请号：US235161

申请日：1994-04-29

申请人： David C. McClure ,  Thomas A. Teel

发明人： David C. McClure ,  Thomas A. Teel

IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C29/50

CPC分类号： G11C29/70 ,  G11C29/24 ,  G11C29/50 ,  G11C11/41

摘要： The redundant elements of an integrated circuit memory device having a plurality of redundant and non-redundant elements such as rows, columns, wordlines, and blocks, may be selectively enabled during a stress test mode so that both redundant elements and non-redundant elements may be stress tested concurrently. Enabling capabilities contained within the redundant element circuitry selectively enables the redundant elements when a stress test signal is equal to a predetermined value, indicative of a stress test mode.

摘要翻译： 具有多个冗余和非冗余元件（诸如行，列，字线和块）的集成电路存储器件的冗余元件可以在压力测试模式期间被选择性地启用，使得冗余元件和非冗余元件可以 同时进行压力测试。 包含在冗余元件电路内的启用功能在压力测试信号等于预定值时，选择性地启用冗余元件，表示压力测试模式。

公开(公告)号：US5521880A

公开(公告)日：1996-05-28

申请号：US251718

申请日：1994-05-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G06F13/42 ,  G11C11/418 ,  G11C8/00

CPC分类号： G11C11/418 ,  G06F13/4239

摘要： A memory system includes two memory arrays coupled to a global data bus via respective address decode circuits. Address control circuitry defaults to the weaker memory array upon receiving a new address such that the stronger memory array will not produce false values on the bus prior to stabilization of the address and proper decode. Consequently, the weaker memory array is not faced with a situation where it must overcome the previous false signal prior to developing the proper output values on the bus.

摘要翻译： 存储器系统包括经由相应地址解码电路耦合到全局数据总线的两个存储器阵列。 接收到新的地址后，地址控制电路默认为较弱的存储器阵列，使得在地址稳定和正确解码之前，较强的存储器阵列将不会在总线上产生错误值。 因此，较弱的存储器阵列并不面临在必须在总线上开发合适的输出值之前克服之前的假信号的情况。