公开(公告)号：US10522367B2

公开(公告)日：2019-12-31

申请号：US15450605

申请日：2017-03-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L21/265 ,  H01L21/322 ,  H01L21/02 ,  H01L23/29 ,  H01L23/31

Abstract: An integrated circuit (IC) device may include a substrate having an active device layer. The integrated circuit may also include a first defect layer. The first defect layer may have a first surface facing a backside of the active device layer. The integrated circuit may further include a second defect layer. The second defect layer may face a second surface opposite the first surface of the first defect layer.

公开(公告)号：US10483287B1

公开(公告)日：2019-11-19

申请号：US16138084

申请日：2018-09-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/08

Abstract: Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.

公开(公告)号：US10460817B2

公开(公告)日：2019-10-29

申请号：US15817474

申请日：2017-11-20

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Wei-Chuan Chen

IPC: G11C7/00 ,  G11C16/34 ,  G11C11/56 ,  G11C14/00 ,  G11C16/04 ,  H01L27/108 ,  H01L29/792 ,  H01L45/00 ,  G06N3/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08 ,  G11C7/18 ,  G11C8/14 ,  H03K19/177

Abstract: Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line.

公开(公告)号：US20190305971A1

公开(公告)日：2019-10-03

申请号：US15944089

申请日：2018-04-03

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Seung Hyuk Kang

IPC: H04L9/32 ,  G11C11/419 ,  G11C7/12

Abstract: Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells enhanced by stress for increased PUF output reproducibility. Stress voltage applied to SRAM bit cells enhances their skew so that the SRAM bit cells output their preferred initial state in subsequent PUF read operations regardless of process variation and other external environmental variations, such as temperature. The application of stress voltage on the SRAM bit cells in a PUF memory array takes advantage of the recognition of aging effect in transistors, where turning transistors on and off over time can increase threshold voltage resulting in lower drive current. Stress voltage can be applied to the SRAM bit cells to bias their threshold voltage to simulate this aging effect to enhance mismatch between transistors in the SRAM bit cell to more fully skew the SRAM bit cells for increased PUF output reproducibility with less susceptible to noise.

公开(公告)号：US10431581B1

公开(公告)日：2019-10-01

申请号：US15966225

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Gengming Tao ,  Bin Yang

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/205 ,  H01L29/225 ,  H01L21/8249 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/737

Abstract: Certain aspects of the present disclosure provide a semiconductor device. One example semiconductor device generally includes a substrate, a well region disposed adjacent to the substrate, a first fin disposed above the well region, a second fin disposed above the substrate, and a gate region disposed adjacent to each of the first fin and the second fin. The semiconductor device may also include at least one third fin disposed above the substrate, a support layer disposed above the at least one third fin, and a compound semiconductor device disposed above the support layer.

公开(公告)号：US10431278B2

公开(公告)日：2019-10-01

申请号：US15676957

申请日：2017-08-14

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

IPC: G11C11/16 ,  G11C5/14 ,  G11C7/04 ,  G11C29/50 ,  H01L27/22 ,  H01L43/08

Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

公开(公告)号：US20190214554A1

公开(公告)日：2019-07-11

申请号：US15868367

申请日：2018-01-11

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Wei-Chuan Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01F10/32

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  H01F10/3254 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Double-patterned magneto-resistive random access memory (MRAM) for reducing magnetic tunnel junction (MTJ) pitch for increased MRAM bit cell density is disclosed. In one aspect, to fabricate MTJs in an MRAM array with reduced MTJ row pitch, a first patterning process is performed to provide separation areas in an MTJ layer between what will become rows of fabricated MTJs, which facilitates MTJs in a given row sharing a common bottom electrode. This reduces the etch depth and etching time needed to etch the individual MTJs in a subsequent step, can reduce lateral projections of sidewalls of the MTJs, thereby relaxing the pitch between adjacent MTJs, and may allow an initial MTJ hard mask layer to be reduced in height. A subsequent second patterning process is performed to fabricate individual MTJs. Additional separation areas are etched between free layers of adjacent MTJs in a given row to fabricate the individual MTJs.

公开(公告)号：US10312244B2

公开(公告)日：2019-06-04

申请号：US15708913

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Bin Yang ,  Gengming Tao

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/165 ,  H01L29/16 ,  H01L21/762 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  G11C11/419 ,  H01L27/07

Abstract: Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

公开(公告)号：US10283650B2

公开(公告)日：2019-05-07

申请号：US15659718

申请日：2017-07-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Bin Yang ,  Gengming Tao

IPC: H01L27/108 ,  H01L29/94 ,  H01L29/66 ,  H01L29/93 ,  H01L29/06

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor offering at least two types of capacitance tuning, as well as techniques for fabricating the same. For example, a CMOS-compatible silicon on insulator (SOI) process with a buried oxide (BOX) layer may provide a transcap with a front gate (above the BOX layer) and a back gate (beneath the BOX layer). The front gate may offer lower voltage, coarse capacitance tuning, whereas the back gate may offer higher voltage, fine capacitance tuning. By offering both types of capacitance tuning, such transcaps may provide greater capacitance resolution. Several variations of transcaps with front gate and back gate tuning are illustrated and described herein.

公开(公告)号：US10164054B2

公开(公告)日：2018-12-25

申请号：US15683530

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Bin Yang ,  Gengming Tao ,  Xia Li ,  Periannan Chidambaram

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L21/768 ,  H01L29/812

Abstract: A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.