公开(公告)号：US10727276B1

公开(公告)日：2020-07-28

申请号：US16422187

申请日：2019-05-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta ,  Christopher Petti

IPC: H01L27/24 ,  H01L43/12 ,  H01L45/00 ,  G11C13/00 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

公开(公告)号：US10726922B2

公开(公告)日：2020-07-28

申请号：US16000237

申请日：2018-06-05

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/08 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10 ,  H01L27/1157 ,  G11C16/26 ,  H01L27/11582 ,  G11C16/24

Abstract: Apparatuses and techniques for fast programming and read operations for memory cells. A group of word lines comprising a selected word line and one or more adjacent word lines are driven with a common voltage signal during program and read operations. The word lines may be permanently connected to one another or connected by a switch. In another approach, the word lines are driven separately by common voltage signals. In a set of blocks, one block of memory cells can be provided with connected word lines to provide a relatively high access speed, while another block of memory cells has disconnected word lines to provide a higher storage density. In another aspect, the memory cells of a word line are divided into portions, and a portion which is closest to a row decoder is reserved for high access speed with a low storage density.

公开(公告)号：US10714198B1

公开(公告)日：2020-07-14

申请号：US16430851

申请日：2019-06-04

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Huai-yuan Tseng

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/08

Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.

公开(公告)号：US20200152282A1

公开(公告)日：2020-05-14

申请号：US16189200

申请日：2018-11-13

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04

Abstract: Techniques are provided to adaptively determine when to begin verify tests for memory cells during a program operation. The memory cells are programmed using a normal programming speed until their threshold voltage exceeds an initial verify voltage. The memory cells are then programmed further using a reduced programming speed until their threshold voltage exceeds a final verify voltage. In one aspect, a count of memory cells which exceeds the initial verify voltage is used to determine when to begin verify tests for a higher data state. In another aspect, a count of the higher state memory cells which exceeds the initial or final verify voltage is used to determine when to begin verify tests for the higher data state. The counted memory cells are not subject to the reduced programming speed.

公开(公告)号：US20200090770A1

公开(公告)日：2020-03-19

申请号：US16143916

申请日：2018-09-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Disclosed herein is related to a system and a method of adjusting a programming pulse for programming memory cells. In one aspect, the system includes a controller that iteratively applies a programming pulse to the memory cells during programming loops. The programming pulse has progressively increasing magnitudes to program different subsets of the memory cells to corresponding target states. The controller determines that a programming loop to program a subset of the memory cells targeted to have a corresponding target state of the target states is performed. The controller counts a number of memory cells of the subset that have not reached the target state. The controller determines a magnitude for a programming pulse to be applied for a subsequent programming loop based on the counted number, and applies, during the subsequent programming loop, the programming pulse with the determined magnitude.

公开(公告)号：US10553298B1

公开(公告)日：2020-02-04

申请号：US16047599

申请日：2018-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/34 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/08

Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

公开(公告)号：US20190378579A1

公开(公告)日：2019-12-12

申请号：US16002793

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/04 ,  G11C7/04 ,  G11C8/08

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

公开(公告)号：US10482985B2

公开(公告)日：2019-11-19

申请号：US16017996

申请日：2018-06-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  H01L27/1157 ,  G11C11/56

Abstract: Apparatuses, systems, methods, and computer program products for a dynamic bias voltage are presented. A monitor circuit is configured to determine whether an erase loop count of an erase operation for data word lines of an erase block satisfies a threshold. A bias circuit is configured to adjust a voltage applied to one or more dummy word lines of an erase block in response to an erase loop count for data word lines satisfying a threshold. An erase circuit is configured to perform one or more subsequent erase loops of an erase operation for data word lines with an adjusted voltage applied to one or more dummy word lines.

公开(公告)号：US20180182463A1

公开(公告)日：2018-06-28

申请号：US15391006

申请日：2016-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Sarath Puthenthermadam ,  Chris Yip

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

公开(公告)号：US09899077B2

公开(公告)日：2018-02-20

申请号：US15588968

申请日：2017-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.