公开(公告)号：US12069846B2

公开(公告)日：2024-08-20

申请号：US17424621

申请日：2019-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Tatsuya Onuki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H10B12/00 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/78651 ,  H01L29/7869

Abstract: A novel memory device is provided. Over a driver circuit layer, N memory layers (N is a natural number greater than or equal to 2) including a plurality of memory cells provided in a matrix are stacked. The memory cell includes two transistors and one capacitor. An oxide semiconductor is used as a semiconductor included in the transistor. The memory cell is electrically connected to a write word line, a selection line, a capacitor line, a write bit line, and a read bit line. The write bit line and the read bit line extend in the stacking direction, whereby the signal propagation distance from the memory cell to the driver circuit layer is shortened.

公开(公告)号：US12063770B2

公开(公告)日：2024-08-13

申请号：US17414614

申请日：2019-11-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tatsuya Onuki

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L29/7869

Abstract: A novel memory device is provided. The memory device includes a transistor and a capacitor device. The transistor includes a first oxide semiconductor; a first conductor and a second conductor provided over a top surface of the first oxide semiconductor; a second oxide semiconductor that is formed over the first oxide semiconductor and is provided between the first conductor and the second conductor; a first insulator provided in contact with the second oxide semiconductor; and a third conductor provided in contact with the first insulator. The capacitor device includes the second conductor; a second insulator over the second conductor; and a fourth conductor over the second insulator. The first oxide semiconductor has a groove deeper than a thickness of each of the first conductor and the second conductor.

公开(公告)号：US11984152B2

公开(公告)日：2024-05-14

申请号：US18206117

申请日：2023-06-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Takahiko Ishizu ,  Tatsuya Onuki

IPC: G11C11/24 ,  G11C11/408 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H10B99/00

CPC classification number: G11C11/4085 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H10B99/00

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US11961916B2

公开(公告)日：2024-04-16

申请号：US17261665

申请日：2019-07-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Tomoaki Atsumi ,  Shunpei Yamazaki

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/78696 ,  H10B12/31

Abstract: A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.

公开(公告)号：US11849584B2

公开(公告)日：2023-12-19

申请号：US17422883

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato

IPC: G11C16/10 ,  H10B43/27 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02 ,  H01L29/24 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02565 ,  H01L29/24 ,  H10B43/40

Abstract: A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.

公开(公告)号：US11742014B2

公开(公告)日：2023-08-29

申请号：US17829579

申请日：2022-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Hajime Kimura ,  Atsushi Miyaguchi ,  Tatsunori Inoue

IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/12 ,  H10B12/00

CPC classification number: G11C11/405 ,  G06F12/0893 ,  H01L27/1225 ,  H10B12/00

Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

公开(公告)号：US11710744B2

公开(公告)日：2023-07-25

申请号：US17365149

申请日：2021-07-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masayuki Sakakura

IPC: H01L27/12 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H10B12/30

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US11670344B2

公开(公告)日：2023-06-06

申请号：US17540314

申请日：2021-12-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki Atsumi ,  Kiyoshi Kato ,  Tatsuya Onuki ,  Shunpei Yamazaki

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

CPC classification number: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/1225 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US11457167B2

公开(公告)日：2022-09-27

申请号：US16616181

申请日：2018-05-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takanori Matsuzaki ,  Kiyoshi Kato

IPC: H04N5/378 ,  H01L27/146 ,  H03K5/24 ,  H04N5/3745 ,  H01L27/12

Abstract: Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to the comparison result. The negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is determined so that comparison is performed. The differential pair includes a first n-channel transistor and a second n-channel transistor each having a gate and a backgate. The first input terminal is electrically connected to the backgate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

公开(公告)号：US11410716B2

公开(公告)日：2022-08-09

申请号：US16962309

申请日：2019-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Hitoshi Kunitake

IPC: G11C8/00 ,  G11C11/408 ,  H01L27/108

Abstract: A novel storage device and a novel semiconductor device are provided.
In the storage device, a cell array including a plurality of memory cells is stacked above a control circuit, and the cell array operates separately in a plurality of blocks. Furthermore, a plurality of electrodes are included between the control circuit and the cell array. The electrode is provided for a corresponding block to overlap with the block, and a potential of the electrode can be changed for each block. The electrode has a function of aback gate of a transistor included in the memory cell, and a potential of the electrode is changed for each block, whereby the electrical characteristics of the transistor included in the memory cell can be changed. Moreover, the electrode can reduce noise caused in the control circuit.