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    Method for forming semiconductor memory device with sacrificial via
    163.
    发明授权
    Method for forming semiconductor memory device with sacrificial via 有权

    公开(公告)号：US11081493B2

    公开(公告)日：2021-08-03

    申请号：US16413859

    申请日：2019-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  G11C5/06

    Abstract: A method for forming a semiconductor memory device is provided. The method includes forming a sacrificial via in a dielectric layer over a substrate, forming a first active layer over the dielectric layer, forming an insulating layer over the first active layer, and forming a second active layer over the insulating layer. The method also includes forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via, removing the sacrificial via to form a via hole in the dielectric layer, and filling the trench and the via hole with a conductive material.

    BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES
    164.
    发明申请
    BIPOLAR SELECTOR WITH INDEPENDENTLY TUNABLE THRESHOLD VOLTAGES 有权

    公开(公告)号：US20210233958A1

    公开(公告)日：2021-07-29

    申请号：US17230222

    申请日：2021-04-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Min Cao ,  Randy Osborne

    IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08

    Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

    3D FERROELECTRIC MEMORY
    167.
    发明申请
    3D FERROELECTRIC MEMORY 有权

    公开(公告)号：US20210126013A1

    公开(公告)日：2021-04-29

    申请号：US16903545

    申请日：2020-06-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin

    IPC: H01L27/11597 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

    Abstract: Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

    Flash Memory Structure and Method of Forming the Same
    169.
    发明申请
    Flash Memory Structure and Method of Forming the Same 审中-公开

    公开(公告)号：US20200258899A1

    公开(公告)日：2020-08-13

    申请号：US16509728

    申请日：2019-07-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Yung-Yu Chen

    IPC: H01L27/11582 ,  H01L23/532

    Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

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