公开(公告)号：US20190051731A1

公开(公告)日：2019-02-14

申请号：US15691717

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/08

Abstract: A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

公开(公告)号：US20190043861A1

公开(公告)日：2019-02-07

申请号：US16149125

申请日：2018-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

公开(公告)号：US20190035743A1

公开(公告)日：2019-01-31

申请号：US16003090

申请日：2018-06-07

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Yi-Wang Zhan ,  Chia-Liang Liao ,  Yu-Cheng Tung ,  Chien-Hao Chen ,  Chia-Hung Wang

IPC: H01L23/544 ,  H01L27/108

CPC classification number: H01L23/544 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/10852 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.

公开(公告)号：US20190027588A1

公开(公告)日：2019-01-24

申请号：US15675380

申请日：2017-08-11

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/3115

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dopping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion. The recessed portion is located between the fin portions. The bottom surface of the recessed portion is lower than the surface of the substrate between the fin portions. The dopping layer is disposed on the sidewall of the fin portions, the surface of the substrate, and the sidewall and the bottom portion of the recessed portion. The dielectric layer is disposed on the dopping layer. The top surface of the dopping layer and the top surface of the dielectric layer are lower than the top surface of each of the fin portions.

公开(公告)号：US20190013381A1

公开(公告)日：2019-01-10

申请号：US15656802

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Ching-Ling Lin

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

公开(公告)号：US10170362B2

公开(公告)日：2019-01-01

申请号：US15472295

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Yu-Cheng Tung ,  Fu-Che Lee ,  Ming-Feng Kuo

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L23/535 ,  H01L29/06 ,  H01L23/528 ,  H01L27/108

Abstract: The present invention provides a method of forming a semiconductor device. First, providing a substrate, and an STI is forming in the substrate to define a plurality of active regions. Then a first etching process is performed to form a bit line contact opening, which is corresponding to one of the active regions. A second etching process is performed to remove a part of the active region and its adjacent STI so a top surface of active region is higher than a top surface of the STI. Next, a bit line contact is formed in the opening. The present invention further provides a semiconductor structure.

公开(公告)号：US10164039B2

公开(公告)日：2018-12-25

申请号：US15283445

申请日：2016-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung

IPC: H01L29/76 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L21/768

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

公开(公告)号：US10147614B1

公开(公告)日：2018-12-04

申请号：US15865162

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiang Li ,  Shao-Hui Wu ,  Hsiao Yu Chia ,  Yu-Cheng Tung

IPC: H01L21/441 ,  H01L21/304 ,  H01L21/768 ,  H01L29/66 ,  H01L29/24 ,  H01L29/78 ,  H01L23/00 ,  H01L29/786

Abstract: A method of manufacturing an oxide semiconductor transistor is provided in the present invention, which includes the step of providing an oxide semiconductor transistor on the front side of a substrate, attaching a wafer on the front side of the substrate, forming a contact hole extending from the back side of the substrate to the oxide semiconductor layer of the oxide semiconductor transistor, and filling the contact hole with metal material to form a back gate of the oxide semiconductor transistor.

公开(公告)号：US20180342613A1

公开(公告)日：2018-11-29

申请号：US15942568

申请日：2018-04-01

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Yu-Cheng Tung ,  Fu-Che Lee

IPC: H01L29/78 ,  H01L21/4757 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/7825 ,  H01L21/0229 ,  H01L21/47573 ,  H01L21/76224 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2221/1057

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and at least a gate trench extending along a first direction formed in the substrate. A gate dielectric layer is formed conformally covering the gate trench. A gate metal is formed on the gate dielectric layer and filling the gate trench. A plurality of intervening structures are arranged along the first direction in a lower portion of the gate trench and disposed between the gate metal and the gate dielectric layer.

公开(公告)号：US20180342581A1

公开(公告)日：2018-11-29

申请号：US16053794

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/66 ,  H01L29/49 ,  H01L29/16 ,  H01L23/535 ,  H01L21/306 ,  H01L29/775

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/30604 ,  H01L23/535 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/4975 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A nanowire transistor includes: a nanowire channel layer on a substrate; a gate structure on and around the nanowire channel layer, wherein the gate structure comprises a high-k dielectric layer on the nanowire channel layer; a first spacer on a lateral sidewall of the gate structure, wherein a lateral sidewall of the first spacer is aligned with a lateral sidewall of the nanowire channel layer; a second spacer on the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer, wherein top surfaces of the first spacer and the second spacer are coplanar and the second spacer contacts the lateral sidewall of the first spacer and the lateral sidewall of the nanowire channel layer directly; and a source/drain structure adjacent to two sides of the second spacer.