公开(公告)号：US20070269588A1

公开(公告)日：2007-11-22

申请号：US11309852

申请日：2006-10-13

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: C23C18/31

CPC classification number: H05K3/0035 ,  H05K3/0038 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/108

Abstract: A method for forming stacked via-holes on a printed circuit board includes the steps of: providing a printed circuit board having a conductive trace formed on a side surface thereof; forming a first copper-clad laminate on the side surface having the conductive trace; forming a number of first copper micro-via in a copper layer of the first copper-clad laminate; forming a second copper-clad laminate on the surface of the copper layer having the first copper micro-via of the first copper-clad laminate; forming a number of second copper micro-via in a copper layer of the second copper-clad laminate by a first laser on the basis of the first copper micro-via, each second copper micro-via being located corresponding to its correspondingly first copper micro-via; and removing corresponding resin layer portions of the first and second copper-clad laminates, using a second laser, to yield the respective stacked via-holes.

Abstract translation: 一种在印刷电路板上形成堆叠的通孔的方法包括以下步骤：提供在其侧表面上形成有导电迹线的印刷电路板; 在具有导电迹线的侧表面上形成第一覆铜层压板; 在第一覆铜层压板的铜层中形成多个第一铜微通孔; 在具有第一覆铜层压板的第一铜微通孔的铜层的表面上形成第二覆铜层压板; 基于第一铜微通孔，通过第一激光在第二覆铜层压板的铜层中形成多个第二铜微通孔，每个第二铜微通孔对应于其相应的第一铜微通孔 -通过; 并使用第二激光器除去第一和第二覆铜层压板的相应树脂层部分，以产生相应的堆叠通孔。

公开(公告)号：US07183593B2

公开(公告)日：2007-02-27

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ge ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L29/86 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US07176537B2

公开(公告)日：2007-02-13

申请号：US11134897

申请日：2005-05-23

Applicant: Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

Inventor： Wen-Chin Lee ,  Chung-Hu Ke ,  Min-Hwa Chi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7839 ,  H01L21/26506 ,  H01L21/28097 ,  H01L21/32155 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66643

Abstract: A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode having a work function of less than about 4.3 eV or greater than about 4.9 eV overlying the gate dielectric, a spacer having a thickness of less than about 100 Å on a side of the gate electrode, and a Schottky source/drain having a work function of less than about 4.3 eV or greater than about 4.9 eV wherein the Schottky source/drain region overlaps the gate electrode. The Schottky source/drain region preferably has a thickness of less than about 300 Å.

Abstract translation: 提供了具有金属/金属硅化物栅极和肖特基源极/漏极的半导体器件及其形成方法。 半导体器件包括覆盖半导体衬底的栅极电介质，金属或金属硅化物栅电极，其功函数小于约4.3eV或大于约4.9eV，覆盖在栅极电介质上，具有小于约100的厚度的间隔物 并且肖特基源/漏极具有小于约4.3eV或大于约4.9eV的功函数，其中肖特基源极/漏极区与栅电极重叠。 肖特基源极/漏极区优选具有小于约的厚度。

公开(公告)号：US07112848B2

公开(公告)日：2006-09-26

申请号：US10939923

申请日：2004-09-13

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC classification number: H01L29/7842 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78639

Abstract: Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion of the thin semiconductor and insulating layers. Source/drain stressors are then formed contacting the source/drain extensions on opposing sides of the pedestal and substantially spanning a height no less than the pedestal.

公开(公告)号：US20060202254A1

公开(公告)日：2006-09-14

申请号：US11077479

申请日：2005-03-10

Applicant: Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

Inventor： Li-Shyue Lai ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC: H01L29/788

CPC classification number: H01L21/28273 ,  H01L29/66825 ,  H01L29/7391 ,  H01L29/8616

Abstract: A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.

公开(公告)号：US20060125121A1

公开(公告)日：2006-06-15

申请号：US11081416

申请日：2005-03-16

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC: H01L31/109

CPC classification number: H01L27/095 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844 ,  H01L29/7841 ,  H01L29/812

Abstract: A tunneling injection based Schottky source/drain memory cell comprising: a first semiconductor layer with a first conductivity type overlying an insulating layer, wherein the first semiconductor acts as a body region; a gate dielectric overlying the semiconductor layer; a gate electrode overlying the gate dielectric; a pair of spacers on sides of the gate electrodes; and a first Schottky barrier junction formed on a source region and a second Schottky barrier junction formed on a drain region on opposing sides of the body region. The source and the regions have an overlapping portion with the gate electrode and length of overlapping portion is preferably greater than about 5 Å. Interfacial layers are formed between the first and the second Schottky barrier regions.

Abstract translation: 一种基于隧道注入的肖特基源/漏存储单元，包括：第一半导体层，其具有覆盖绝缘层的第一导电类型，其中所述第一半导体作为体区; 覆盖半导体层的栅极电介质; 覆盖栅极电介质的栅电极; 栅电极侧面的一对间隔物; 以及形成在源区域上的第一肖特基势垒结和形成在身体区域的相对侧上的漏极区域上的第二肖特基势垒结。 源极和区域与栅电极具有重叠部分，并且重叠部分的长度优选大于约。 在第一和第二肖特基势垒区之间形成界面层。

公开(公告)号：US20060114229A1

公开(公告)日：2006-06-01

申请号：US10996459

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/08

CPC classification number: G06F3/0362 ,  G06F3/0383

Abstract: A magnetic oscillation metric controller applied to computer peripheral or electronic communication system essentially operating on a scrolling wheel for lateral metric control to provide precise, consistent, reliable and programmable adjustment oscillation sensitivity by driving a permanent magnet to generate signals of changed magnetic fields resulted from displacement; and retrieving the data of changed signals for achieving metric control purpose.

Abstract translation: 应用于计算机外围或电子通信系统的磁振荡度量控制器，其基本上在用于横向度量控制的滚动轮上操作，以通过驱动永久磁体以产生由位移产生的变化的磁场的信号来提供精确，一致，可靠和可编程的调节振荡灵敏度 ; 以及检索改变信号的数据以达到度量控制目的。

公开(公告)号：US07052964B2

公开(公告)日：2006-05-30

申请号：US11081919

申请日：2005-03-16

Applicant: Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Chih-Hsin Ko ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203

Abstract: A semiconductor device includes a region of semiconductor material with first and second isolation trenches formed therein. The first isolation trench is lined with a first material having a low oxygen diffusion rate and is filled with an insulating material. The second isolation trench is not lined with the first material but is filled with an insulating material. A first transistor is formed adjacent the first isolation region and a second transistor formed adjacent the second isolation region.

Abstract translation: 半导体器件包括其中形成有第一和第二隔离沟槽的半导体材料区域。 第一隔离槽衬有具有低氧扩散速率的第一材料并填充绝缘材料。 第二隔离槽不是衬有第一材料，而是用绝缘材料填充。 形成在第一隔离区域附近的第一晶体管和与第二隔离区域相邻形成的第二晶体管。

公开(公告)号：US20060081875A1

公开(公告)日：2006-04-20

申请号：US10967917

申请日：2004-10-18

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L31/109 ,  H01L31/0328 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20060038199A1

公开(公告)日：2006-02-23

申请号：US10922087

申请日：2004-08-19

Applicant: Wen-Chin Lee

Inventor： Wen-Chin Lee

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L29/739

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing microelectronic devices including forming a silicon substrate with first and second wells of different dopant characteristics, forming a first strained silicon-germanium-carbon layer of a first formulation proximate to the first well, and forming a second strained silicon-germanium-carbon layer of a second formulation distinct from the first formulation proximate to the second well. Capping and insulating layers, gate structures, spacers, and sources and drains are then formed, thereby creating a CMOS device with independently strained channels.