公开(公告)号：US07087947B2

公开(公告)日：2006-08-08

申请号：US10957688

申请日：2004-10-05

Applicant: Brian S. Lee ,  Chih-Yu Lee

Inventor： Brian S. Lee ,  Chih-Yu Lee

IPC: H01L27/108

CPC classification number: H01L21/32139 ,  G03F1/30 ,  H01L27/10861 ,  H01L27/10891

Abstract: An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip. By using the alternating phase shift mask to pattern gate-lines or active areas in a DRAM array, no unwanted image is created in the DRAM array and only one exposure is needed to achieve high resolution requirement.

Abstract translation: 具有暗环的交替相移掩模，用交替相移掩模制造的存储器阵列，以及制造存储器的方法。 掩模中的暗环总是将具有180°相位差的第一区域与具有0°相位差的第二区域分开，以限定DRAM芯片中的有源区域或栅极线。 通过使用交替相移掩模来对DRAM阵列中的栅极线或有源区进行图案化，在DRAM阵列中不产生不需要的图像，并且仅需要一次曝光来实现高分辨率要求。

公开(公告)号：US07071115B2

公开(公告)日：2006-07-04

申请号：US10772932

申请日：2004-02-04

Applicant: Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

Inventor： Chunchieh Huang ,  Chia-Shun Hsiao ,  Jin-Ho Kim ,  Kuei-Chang Tsai ,  Barbara Haselden ,  Daniel C. Wang

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/44 ,  H01L21/76

CPC classification number: H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

Abstract: In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

公开(公告)号：US07060565B2

公开(公告)日：2006-06-13

申请号：US10631452

申请日：2003-07-30

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11534

Abstract: A memory cell (110) has a select gate (140) and at least two floating gates (160). A gate dielectric (150) for the floating gates (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of the select gate (140). The dielectric thickness on the select gate is controlled by the dopant concentration in the select gate. Other features are also provided.

Abstract translation: 存储单元（110）具有选择栅极（140）和至少两个浮置栅极（160）。 用于浮动栅极（160）的栅极电介质（150）通过热氧化同时作为选择栅极（140）的表面上的电介质形成。 选择栅极上的电介质厚度由选择栅极中的掺杂剂浓度控制。 还提供其他功能。

公开(公告)号：US20060115952A1

公开(公告)日：2006-06-01

申请号：US10998929

申请日：2004-11-30

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L21/00

CPC classification number: H01L29/66181 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10867 ,  H01L28/91 ,  H01L29/417 ,  H01L29/945

Abstract: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

Abstract translation: 描述形成多层电极电容器的方法。 在衬底或绝缘体层中形成沟槽。 两组导电层沉积在沟槽的内表面上。 第一组导电层彼此电连接，第二组导电层也相互电连接。 第二组导电层中的每一个插入在两个第一导电层之间，并且电介质层插在两个导电层之间以形成多层电极电容器。

公开(公告)号：US07053438B2

公开(公告)日：2006-05-30

申请号：US10972159

申请日：2004-10-21

Applicant: Yi Ding

Inventor： Yi Ding

IPC: H01L29/76

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: In fabrication of a nonvolatile memory cell having two floating gates, one or more peripheral transistor gates are formed from the same layer (140) as the select gate. The gate dielectric (130) for these peripheral transistors and the gate dielectric (130) for the select gates are formed, simultaneously. In a nonvolatile memory having a memory cell with two floating gates, the gate dielectric (130) for the peripheral transistors and the gate dielectric (130) for the select gates (140) have the same thickness.

Abstract translation: 在具有两个浮置栅极的非易失性存储单元的制造中，与选择栅极相同的层（140）形成一个或多个外围晶体管栅极。 同时形成用于这些外围晶体管的栅极电介质（130）和用于选择栅极的栅极电介质（130）。 在具有具有两个浮置栅极的存储单元的非易失性存储器中，用于外围晶体管的栅极电介质（130）和选择栅极（140）的栅极电介质（130）具有相同的厚度。

公开(公告)号：US07049245B2

公开(公告)日：2006-05-23

申请号：US10660821

申请日：2003-09-12

Applicant: Fang-Yu Yeh ,  Chi Lin ,  Chia-Yao Chen

Inventor： Fang-Yu Yeh ,  Chi Lin ,  Chia-Yao Chen

IPC: H01L21/302

CPC classification number: H01L21/28061 ,  H01L21/32137 ,  H01L21/32139

Abstract: A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.

Abstract translation: 一种制造半导体器件的方法，包括限定半导体衬底，在半导体衬底上形成栅极氧化物，在栅极氧化物上形成多晶硅层，在多晶硅层上形成硅化钨层; 在所述硅化钨层上提供掩模，限定所述掩模以暴露所述硅化钨层的至少一部分，用第一蚀刻剂蚀刻所述暴露的硅化钨层，其中保留一些硅化钨层，用 第二蚀刻剂以暴露多晶硅层的至少一部分，退火硅化钨层，蚀刻暴露的多晶硅层，以及氧化硅化钨层和多晶硅层的侧壁。

公开(公告)号：US20060102947A1

公开(公告)日：2006-05-18

申请号：US11290432

申请日：2005-12-01

Applicant: Yung Wu

Inventor： Yung Wu

IPC: H01L29/94

CPC classification number: H01L21/26506 ,  H01L21/26586 ,  H01L27/10867 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66181

Abstract: A DRAM memory cell and a method of making a DRAM memory cell are provided. The DRAM memory cell includes a semiconductor substrate, including a trench formed therein and a buried plate region, at least a first doped region and a second doped region provided on a sidewall of the trench above the buried plate region in the substrate, where the first doped region contains carbon and the second doped region contains germanium provided in a portion of the first region, a dielectric layer formed on the bottom and sidewall of the trench, at least one polysilicon layer deposited in the trench and on the dielectric layer to cover the dielectric layer, and a transistor formed on a surface of the semiconductor substrate.

公开(公告)号：US20060086962A1

公开(公告)日：2006-04-27

申请号：US10971133

申请日：2004-10-25

Applicant: Hsiao Wu

Inventor： Hsiao Wu

IPC: H01L21/8242 ,  H01L29/76

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: The present invention discloses a stacked capacitor having interdigital electrodes and method for preparing the same. The stacked capacitor comprises a first interdigital electrode, a second interdigital electrode and a dielectric material sandwiched between the first interdigital electrode and the second interdigital electrode. The first and the second interdigital electrodes comprise a body and a plurality of fingers electrically connected to the body, and the dielectric material can be silicon nitride or silicon oxide. Preferably, fingers of the first interdigital electrode are made of titanium nitride, while fingers of the second interdigital electrode are made of polysilicon. The body of the first and the second interdigital electrodes are preferably made of titanium nitride.

Abstract translation: 本发明公开了一种具有叉指电极的叠层电容器及其制备方法。 叠层电容器包括夹在第一叉指电极和第二叉指电极之间的第一叉指电极，第二指状电极和介电材料。 第一和第二叉指电极包括主体和电连接到主体的多个指状物，并且电介质材料可以是氮化硅或氧化硅。 优选地，第一叉指电极的指状物由氮化钛制成，而第二指状电极的指状物由多晶硅制成。 第一和第二叉指电极的主体优选地由氮化钛制成。

公开(公告)号：US07026209B2

公开(公告)日：2006-04-11

申请号：US10605199

申请日：2003-09-15

Applicant: Ting-Shing Wang

Inventor： Ting-Shing Wang

IPC: H01L21/8242

CPC classification number: H01L27/10832 ,  H01L27/0207 ,  H01L27/10841 ,  H01L27/10861 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/10888 ,  H01L29/945

Abstract: A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The vertical transistor includes a first doped region, a second doped region, a gate and a gate insulating layer. The first doped region is located in the sidewall and is coupled with the capacitor. The second doped region is located in a top portion of the pillar. The gate is disposed on the sidewall of the pillar between the first and the second doped regions, and the gate insulating layer is disposed between the sidewall and the gate.

Abstract translation: 描述了动态随机存取存储器（DRAM）单元，其包括衬底上的半导体柱，柱的侧壁的下部的电容器和柱的侧壁上部的垂直晶体管。 垂直晶体管包括第一掺杂区，第二掺杂区，栅极和栅极绝缘层。 第一掺杂区域位于侧壁中并与电容器耦合。 第二掺杂区位于柱的顶部。 栅极设置在第一和第二掺杂区域之间的柱的侧壁上，并且栅极绝缘层设置在侧壁和栅极之间。

公开(公告)号：US20060064194A1

公开(公告)日：2006-03-23

申请号：US10974715

申请日：2004-10-28

Applicant: Yung-Yao Lee

Inventor： Yung-Yao Lee

IPC: G06F19/00

CPC classification number: G03F7/70633 ,  G03F7/70533 ,  G03F9/7003 ,  G03F9/7011 ,  G03F9/7019 ,  G03F9/7046

Abstract: A system for determining lithography overlay offsets is described. The system comprises a first database, a second database, and a controller. The first database stores operation records of lots processed consecutively by an exposure tool, wherein each lot corresponds to a layer of a product, and the operation records pertain to a subsequent lot Lk and a previous lot Lk-1 corresponding to products A and B, respectively. The second database stores overlay information of lots corresponding to the products A and B, comprising overlay information DA,X and DB,Y corresponding to Xth and yth records of products A and B. The controller determines the overlay offset corresponding to lot Lk according to the overlay information DA,X and DB,Y.

Abstract translation: 描述了一种用于确定光刻叠加偏移的系统。 该系统包括第一数据库，第二数据库和控制器。 第一数据库存储由曝光工具连续处理的批次的操作记录，其中每个批对应于产品的层，并且操作记录与随后的批次L＆lt; k＆gt;和之前的批次L < SUB> k-1 分别对应于产品A和B. 第二数据库存储与产品A和B相对应的批次的重叠信息，其中包括对应于X'的叠加信息D A，X和D B，Y， / SUP>和第个产品A和B的记录。控制器根据重叠信息D A，X，X确定与批次L＆lt; k＆gt;相对应的叠加偏移 和/或B B，Y 。