公开(公告)号：US20220262415A1

公开(公告)日：2022-08-18

申请号：US17668571

申请日：2022-02-10

Applicant: Rambus Inc.

Inventor： Sreeja MENON ,  Charles J. WILSON ,  Sudhir Kumar Katla SHETTY ,  Larry ARBUTHNOT ,  Nikhil Raghavendra RAO

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C29/42

Abstract: System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information.

公开(公告)号：US20220253378A1

公开(公告)日：2022-08-11

申请号：US17728791

申请日：2022-04-25

Applicant: Rambus Inc.

Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

IPC: G06F12/02 ,  G11C7/22 ,  G11C7/10 ,  G11C8/10

Abstract: A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

公开(公告)号：US20220245073A1

公开(公告)日：2022-08-04

申请号：US17677714

申请日：2022-02-22

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US20220238177A1

公开(公告)日：2022-07-28

申请号：US17720054

申请日：2022-04-13

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

公开(公告)号：US20220223224A1

公开(公告)日：2022-07-14

申请号：US17556363

申请日：2021-12-20

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US11386941B1

公开(公告)日：2022-07-12

申请号：US17117411

申请日：2020-12-10

Applicant: Rambus Inc.

Inventor： Neeraj Purohit ,  Navin Kumar Mishra ,  Anirudha Shelke

IPC: H03K5/135 ,  G11C7/22 ,  G11C7/10

Abstract: A gating signal for masking overhead transitions in a data-strobe signal is generated adaptively based on timing events in the incoming data-strobe signal itself to yield a gating window that opens and closes deterministically with respect to active edges of the data-strobe signal.

公开(公告)号：US11379136B2

公开(公告)日：2022-07-05

申请号：US17075357

申请日：2020-10-20

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US20220209999A1

公开(公告)日：2022-06-30

申请号：US17573471

申请日：2022-01-11

Applicant: Rambus Inc.

Inventor： Vladimir M. Stojanovic ,  Andrew C. Ho ,  Anthony Bessios ,  Fred F. Chen ,  Elad Alon ,  Mark A. Horowitz

IPC: H04L25/49 ,  H04L25/02 ,  H04L25/03 ,  H04L25/06 ,  H04B1/04

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

公开(公告)号：US20220208267A1

公开(公告)日：2022-06-30

申请号：US17573456

申请日：2022-01-11

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Nigel Alvares ,  Sarvagya Kochak

IPC: G11C14/00 ,  G06F12/0804

Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

公开(公告)号：US11372784B2

公开(公告)日：2022-06-28

申请号：US16709506

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Pravin Kumar Venkatesan ,  Liji Gopalakrishnan ,  Kashinath Ullhas Prabhu ,  Makarand Ajit Shirasgaonkar

IPC: G06F13/16

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.