公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US12165714B2

公开(公告)日：2024-12-10

申请号：US17916927

申请日：2021-04-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Bin Chen ,  Youhui Li ,  Ming Gu ,  Xinmiao Zhao ,  Hao Wang ,  Shuming Guo ,  Zongchuan Wang ,  Nan Zhang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory, comprising a negative voltage providing unit, which is used for providing a first negative voltage to a word line during a read operation, and comprises: a clamping unit that comprises an input end, a control end and an output end, wherein the input end is coupled to a common ground end of the memory, and the control end is used for receiving a first signal; an energy storage capacitor, a first end of which is coupled to the output end, and a second end that is used for receiving a second signal; and a negative voltage providing end which is coupled to the first end, wherein the clamping unit is used for: pulling the voltage at the output end to the voltage at the input end when the first signal is “0”; and clamping the output end at a clamping voltage when the first signal is “1”.

公开(公告)号：US12154983B2

公开(公告)日：2024-11-26

申请号：US17639359

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong He

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

Abstract: The present disclosure provides a lateral double-diffused metal oxide semiconductor device and a manufacturing method thereof, and an electronic apparatus. The method includes: providing a semiconductor substrate, and forming a drift region and a body region in the semiconductor substrate; forming a drain region in the drift region, forming a source region in the body region, and forming, on the body region, a gate structure extending to the drift region; implanting ions of a first type, so as to form, at a bottom of the drift region, first ion implantation regions extending along a direction from the gate structure to the drain region; forming, above the first ion implantation regions, a plurality of mutually spaced deep trench structures and fin structures between adjacent ones of the deep trench structures; and implanting ions of a second type in the deep trench structures to form second ion implantation regions.

公开(公告)号：US12130649B2

公开(公告)日：2024-10-29

申请号：US17799459

申请日：2020-12-09

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Youhui Li ,  Lijuan Zhu

IPC: G11C16/30 ,  G05F3/24

CPC classification number: G05F3/24 ,  G11C16/30

Abstract: A bias current generation circuit and a flash memory. The bias current generation circuit includes a voltage source, a switching circuit and a current generation circuit. The voltage source is configured to provide a voltage for generating a bias current. An input terminal of the switching circuit is connected to the voltage source, a control terminal of the switching circuit is configured to receive a control signal. The current generation circuit includes a first MOS transistor and a second MOS transistor, an input terminal and a control terminal of the first MOS transistor are connected to an output terminal of the switching circuit, an output terminal of the first MOS transistor is connected to an input terminal and a control terminal of the second MOS transistor, and an output terminal of the second MOS transistor is grounded.

公开(公告)号：US12015025B2

公开(公告)日：2024-06-18

申请号：US17265549

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L29/0692 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

公开(公告)号：US20240136413A1

公开(公告)日：2024-04-25

申请号：US18277658

申请日：2021-07-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： CHUNXU LI ,  FENG LIN ,  SHUXIAN CHEN ,  HONGFENG JIN ,  HUAJUN JIN ,  GANG HUANG ,  YU HUANG ,  BIN YANG

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: A laterally diffused metal oxide semiconductor device and a preparation method thereof are disclosed. The semiconductor device includes: a substrate; a body region having a first conductivity type and formed in the substrate; a drift region, having a second conductivity type, formed in the substrate and adjacent to the body region; a field plate structure, formed on the drift region, a lower surface of an end of the field plate structure close to the body region being flush with the upper surface of the substrate, and the end of the field plate structure close to the body region also having an upwardly extending inclined surface; and a drain region, having a second conductivity type, formed in an upper layer of the drift region, and in contact with the end of the field plate structure away from the body region.

公开(公告)号：US11923453B2

公开(公告)日：2024-03-05

申请号：US17631287

申请日：2020-08-18

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun Jin ,  Chunxu Li

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L29/0611 ,  H01L29/401 ,  H01L29/404 ,  H01L29/66681

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

公开(公告)号：US20240072178A1

公开(公告)日：2024-02-29

申请号：US18262083

申请日：2022-03-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Hua SONG ,  Nailong HE ,  Sen ZHANG

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/872 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7394 ,  H01L29/7835

Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.

公开(公告)号：US20240047212A1

公开(公告)日：2024-02-08

申请号：US18258902

申请日：2021-07-27

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Hongfeng JIN ,  Ruibin CAO ,  Feng LIN ,  Xiang QIN ,  Yu HUANG ,  Chunxu LI

IPC: H01L21/265 ,  H01L29/66 ,  H01L29/78 ,  H01L21/027 ,  H01L21/266

CPC classification number: H01L21/2652 ,  H01L29/66681 ,  H01L29/7816 ,  H01L21/0274 ,  H01L21/266

Abstract: A semiconductor device and a manufacturing method therefor are disclosed. The method includes: providing a substrate of a first conductivity type; forming doped regions of a second conductivity type in the substrate, the doped regions including adjacent first and second drift regions, wherein the second conductivity type is opposite to the first conductivity type; forming a polysilicon film on the substrate, the polysilicon film covering the doped regions; forming patterned photoresist on the polysilicon film, which covers the first and second drift regions, and in which the polysilicon film above a reserved region for a body region between the first and second drift regions is exposed; and forming the body region of the first conductivity type in the reserved region by performing a high-energy ion implantation process, the body region having a top surface that is flush with top surfaces of the doped regions, the body region having a bottom surface that is not higher than bottom surfaces of the doped regions. The problem of morphological changes possibly experienced by the photoresist due to a high temperature in an etching process, which may lead to an impaired effect of the high-energy ion implantation process, can be circumvented.

公开(公告)号：US11770076B2

公开(公告)日：2023-09-26

申请号：US17420866

申请日：2020-06-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Minggang Chen ,  Wanqing Yang ,  Dejin Wang ,  Rui Jiang ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/38 ,  H02M1/34

CPC classification number: H02M3/33569 ,  H02M1/342 ,  H02M1/38 ,  H02M3/33523

Abstract: Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.