公开(公告)号：US07338903B2

公开(公告)日：2008-03-04

申请号：US10910182

申请日：2004-08-02

Applicant: Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/44

CPC classification number: H01L21/76831 ,  H01L21/02046 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

Abstract: A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Abstract translation: 在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。 可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。 当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。

公开(公告)号：US07250683B2

公开(公告)日：2007-07-31

申请号：US11056758

申请日：2005-02-11

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

Abstract translation: 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US07154178B2

公开(公告)日：2006-12-26

申请号：US10918816

申请日：2004-08-13

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/40

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层是通过沉积氮化钨底层，然后沉积原位SiH 4 / NH 3或SiH 4 H / 浸泡形成WSiN层，并沉积钨的最终顶层。 本发明用于在用于逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US20050263902A1

公开(公告)日：2005-12-01

申请号：US11174189

申请日：2005-07-01

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L21/768 ,  H01L29/40 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

公开(公告)号：US20050263891A1

公开(公告)日：2005-12-01

申请号：US11100912

申请日：2005-04-07

Applicant: Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

Inventor： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76867

Abstract: A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.

Abstract translation: 提供了一种用于半导体器件的镶嵌结构。 在一个实施例中，镶嵌结构包括在通孔上形成的沟槽，其将沟槽电耦合到下面的导电层，使得沟槽具有变化的宽度。 通孔排列有第一阻挡层。 沿着通孔底部的第一阻挡层被去除，使得形成在下面的导电层中的凹陷。 沿着通孔底部形成的凹槽使得较窄沟槽下面的凹陷大于形成在较宽沟槽下方的凹陷。 在另一个实施例中，然后可以在第一阻挡层上形成第二阻挡层。 在该实施例中，导电层的一部分可插入在第一阻挡层和第二阻挡层之间。

公开(公告)号：US06864670B2

公开(公告)日：2005-03-08

申请号：US10442118

申请日：2003-05-21

Applicant: Jr-Hong Ouyang ,  Hui-Chuan Lai ,  Jing-Cheng Lin

Inventor： Jr-Hong Ouyang ,  Hui-Chuan Lai ,  Jing-Cheng Lin

IPC: H02M3/00 ,  H05K1/02 ,  G05F1/59

CPC classification number: H02M3/00 ,  H05K1/0216 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A method for eliminating noise interference and acoustic noise by a printed circuit board ground plane layout is disclosed. The method is applied to a circuit system having multiple outputs, wherein the circuit system has a first power converting module, a second power converting module and a printed circuit board. The first power converting module and the second power converting module respectively includes a first ground pin group and a second ground pin group. The method includes the steps of (a) connecting each ground pin of the first ground pin group to a respective solder point and connecting each solder point to a first node, and connecting each ground pin of the second ground pin group to a respective solder point and connecting each solder point to a second node, and (b) connecting the first node and the second node to a common node and connecting the common node to a solder point of a common ground terminal on the printed circuit board ground plane.

Abstract translation: 公开了一种通过印刷电路板接地平面布局消除噪声干扰和声学噪声的方法。 该方法应用于具有多个输出的电路系统，其中电路系统具有第一电力转换模块，第二电力转换模块和印刷电路板。 第一电力转换模块和第二电力转换模块分别包括第一接地引脚组和第二接地引脚组。 该方法包括以下步骤：（a）将第一接地引脚组的每个接地引脚连接到相应的焊点并将每个焊接点连接到第一节点，并将第二接地引脚组的每个接地引脚连接到相应的焊点 并且将每个焊接点连接到第二节点，以及（b）将所述第一节点和所述第二节点连接到公共节点，并将所述公共节点连接到所述印刷电路板接地层上的公共接地端子的焊接点。

公开(公告)号：US20050029665A1

公开(公告)日：2005-02-10

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L21/31 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US06806192B2

公开(公告)日：2004-10-19

申请号：US10350837

申请日：2003-01-24

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US06342448B1

公开(公告)日：2002-01-29

申请号：US09583401

申请日：2000-05-31

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L2144

CPC classification number: H01L21/76846 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76873

Abstract: A method for forming an improved TaN copper barrier for a copper damascene process is described which has improved adhesion to low-k dielectric layers and also improves the wetting of a copper seed layer deposited over it thereby improving the structure of the copper seed layer which is critical to achieving uniform, high quality electrochemical copper deposition. The copper barrier is a composite structure having an lower thin Ta rich TaN portion which mixes into and reacts with the surface of the low-k dielectric layer, forming a strongly bonded transition layer between the low-k material and the remaining portion of the barrier layer. The presence of the transition layer causes compressive film stress rather than tensile stress as found in the conventional TaN barrier. As a result, the barrier layer does not delaminate from the low-k layer during subsequent processing. A second thick central portion of the barrier layer is formed of stoichiometric TaN which benefits subsequent CMP of the copper damascene structure. An upper thin Ta portion improves barrier wetting to the copper seed layer. The three sections of the laminar barrier are sequentially deposited in a single pumpdown operation by IMP sputtering from a Ta target.

Abstract translation: 描述了一种用于形成用于铜镶嵌工艺的改进的TaN铜阻挡层的方法，其具有改善的对低k电介质层的粘附性，并且还改善了沉积在其上的铜籽晶层的润湿，从而改善了铜籽晶层的结构， 对于实现均匀，高质量的电化学铜沉积至关重要。 铜屏障是具有较低的Ta Ta薄部分的复合结构，其混合并与低k电介质层的表面反应，在低k材料与阻挡层的剩余部分之间形成牢固结合的过渡层 层。 过渡层的存在导致压缩膜应力而不是常规TaN阻挡层中的拉伸应力。 结果，在随后的处理期间，阻挡层不会从低k层分层。 阻挡层的第二厚中心部分由化学计量的TaN形成，这有利于铜镶嵌结构的后续CMP。 上部薄的Ta部分改善了对铜种子层的屏障润湿。 层状阻挡层的三个部分通过来自Ta靶的IMP溅射在单次抽运操作中依次沉积。

公开(公告)号：US09691706B2

公开(公告)日：2017-06-27

申请号：US13452140

申请日：2012-04-20

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Jui-Pin Hung

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/544 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/742 ,  H01L24/82 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2223/54426 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/24991 ,  H01L2224/82005 ,  H01L2224/82106 ,  H01L2224/8213 ,  H01L2224/82132 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/19 ,  H01L2924/00

Abstract: A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line.