公开(公告)号：US20210043627A1

公开(公告)日：2021-02-11

申请号：US17082434

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Joseph STEIGERWALD ,  Tahir GHANI ,  Oleg GOLONZKA

IPC: H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US20200303509A1

公开(公告)日：2020-09-24

申请号：US16362510

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Rishabh MEHANDRU ,  Tahir GHANI ,  Stephen CEA

IPC: H01L29/417 ,  H01L23/48 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.

公开(公告)号：US20200273998A1

公开(公告)日：2020-08-27

申请号：US16646124

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Karthik JAMBUNATHAN ,  Biswajeet GUHA ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20200251387A1

公开(公告)日：2020-08-06

申请号：US16819590

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Mark T. BOHR ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Subhash M. JOSHI ,  Joseph M. STEIGERWALD ,  Jason W. KLAUS ,  Jack HWANG ,  Ryan MACKIEWICZ

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/285 ,  H01L21/28 ,  H01L29/45 ,  H01L29/16 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/283 ,  H01L29/78 ,  H01L29/49

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20200219978A1

公开(公告)日：2020-07-09

申请号：US16238783

申请日：2019-01-03

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having oxide sub-fins, and methods of fabricating gate-all-around integrated circuit structures having oxide sub-fins, are described. For example, an integrated circuit structure includes an oxide sub-fin structure having a top and sidewalls. An oxidation catalyst layer is on the top and sidewalls of the oxide sub-fin structure. A vertical arrangement of nanowires is above the oxide sub-fin structure. A gate stack is surrounding the vertical arrangement of nanowires and on at least the portion of the oxidation catalyst layer on the top of the oxide sub-fin structure.

公开(公告)号：US20200152738A1

公开(公告)日：2020-05-14

申请号：US16740132

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20200075771A1

公开(公告)日：2020-03-05

申请号：US16122284

申请日：2018-09-05

Applicant: Intel Corporation

Inventor： Mauro J. KOBRINSKY ,  Stephanie BOJARSKI ,  Babita DHAYAL ,  Biswajeet GUHA ,  Tahir GHANI

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238

Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

公开(公告)号：US20200006576A1

公开(公告)日：2020-01-02

申请号：US16024701

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY

IPC: H01L29/786 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006069A1

公开(公告)日：2020-01-02

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L27/12 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20190326391A1

公开(公告)日：2019-10-24

申请号：US16398995

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Milton Clair WEBB ,  Mark BOHR ,  Tahir GHANI ,  Szuya S. LIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417

Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.