公开(公告)号：US20210035630A1

公开(公告)日：2021-02-04

申请号：US17074690

申请日：2020-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Changhyun Lee ,  Akira Goda ,  William C. Filipiak

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: One embodiment of a method for programming multiple-level memory cells includes programming lower page data to memory cells in a first pass of a multiple-pass programming operation. The method includes programming higher page data to the memory cells in a second pass of the multiple-pass programming operation such that higher page data subject to the programmed lower page data is programmed prior to higher page data subject to erase data.

公开(公告)号：US20210027839A1

公开(公告)日：2021-01-28

申请号：US17067550

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US10903223B2

公开(公告)日：2021-01-26

申请号：US16248248

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/115 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US10818357B2

公开(公告)日：2020-10-27

申请号：US16518687

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  H01L27/115 ,  H01L49/02 ,  G11C11/56 ,  G11C16/08 ,  G11C16/34 ,  H01L27/105

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

公开(公告)号：US10783967B2

公开(公告)日：2020-09-22

申请号：US16237337

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US10325661B2

公开(公告)日：2019-06-18

申请号：US15686510

申请日：2017-08-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yijie Zhao ,  Akira Goda

IPC: G11C11/34 ,  G11C16/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.

公开(公告)号：US20190122737A1

公开(公告)日：2019-04-25

申请号：US16227874

申请日：2018-12-20

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: G11C16/26 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/11524 ,  G11C16/10 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C7/1096 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.

公开(公告)号：US10153049B2

公开(公告)日：2018-12-11

申请号：US15722188

申请日：2017-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian Caillat ,  Akira Goda

IPC: G11C16/10 ,  G11C8/12 ,  G11C16/34 ,  G11C16/14 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device during an erase operation. The memory block of memory cells includes a plurality of memory segments and a corresponding plurality of first select gate control lines. Each memory segment includes a plurality of memory sub-blocks that share a respective one of the first select gate control lines. The method includes applying a first bias voltage to the respective first select gate control line of a first one of the memory segments that has failed an erase verify operation to facilitate erasing the first memory segment during the erase operation, and applying a second bias voltage different from the first bias voltage to the respective first select gate control line of a second one of the memory segments that has passed the erase verify operation to facilitate inhibiting erasing of the second memory segment during the erase operation.

公开(公告)号：US10147494B2

公开(公告)日：2018-12-04

申请号：US15933498

申请日：2018-03-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: Apparatus including an array of memory cells and a controller configured to apply a particular programming pulse to a plurality of memory cells having a first subset of memory cells having respective desired data states that are lower than a particular data state and a second subset of memory cells having respective desired data states that are higher than or equal to the particular data state, to at least partially inhibit each memory cell of the first subset of memory cells from programming while not inhibiting any memory cell of the second subset of memory cells from programming and while applying the particular programming pulse, then to apply a subsequent programming pulse while not inhibiting any memory cell of the first subset of memory cells from programming other than any memory cell of the first subset of memory cells having its respective desired data state equal to a lowest data state, and while not inhibiting any memory cell of the second subset of memory cells from programming.

公开(公告)号：US20180342298A1

公开(公告)日：2018-11-29

申请号：US16036549

申请日：2018-07-16

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Haitao Liu ,  Changhyun Lee

IPC: G11C16/04 ,  H01L49/02 ,  H01L27/115 ,  H01L27/105 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  H01L27/1052 ,  H01L27/115 ,  H01L28/00

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.