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    SIGNAL DROP COMPENSATED MEMORY
    171.
    发明申请
    SIGNAL DROP COMPENSATED MEMORY 有权

    公开(公告)号：US20250087289A1

    公开(公告)日：2025-03-13

    申请号：US18960471

    申请日：2024-11-26

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C29/42 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/44

    Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.

    FORWARD LOOKING ALGORITHM FOR VERTICAL INTEGRATED CROSS-POINT ARRAY MEMORY
    172.
    发明申请
    FORWARD LOOKING ALGORITHM FOR VERTICAL INTEGRATED CROSS-POINT ARRAY MEMORY 有权

    公开(公告)号：US20250022507A1

    公开(公告)日：2025-01-16

    申请号：US18903900

    申请日：2024-10-01

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C13/00

    Abstract: Systems and methods for reading a first and second plurality of memory cells include applying a first ramping voltage with a first increment for each ramping step to read the first plurality of cells, counting, among the first plurality of cells at each ramping step, a first number of logic 1 cells, comparing the first number with a threshold at each ramping step of the first ramping voltage, determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the threshold for the first time, applying a second voltage lower than the first voltage to read the second plurality of cells, and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment lower than the first predetermined increment for each ramping step to read the second plurality of cells.

    DECODER ARCHITECTURE FOR MEMORY DEVICE
    173.
    发明申请
    DECODER ARCHITECTURE FOR MEMORY DEVICE 有权

    公开(公告)号：US20250014640A1

    公开(公告)日：2025-01-09

    申请号：US18768922

    申请日：2024-07-10

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Jeffrey E. Koelling ,  Hari Giduturi ,  Riccardo Muzzetto ,  Corrado Villa

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

    Forward looking algorithm for vertical integrated cross-point array memory
    174.
    发明授权
    Forward looking algorithm for vertical integrated cross-point array memory 有权

    公开(公告)号：US12112801B2

    公开(公告)日：2024-10-08

    申请号：US17897021

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C7/14 ,  G11C13/00 ,  G11C16/28

    CPC classification number: G11C13/0035 ,  G11C13/0004 ,  G11C13/004

    Abstract: Systems and methods for reading a first and second plurality of memory cells include applying a first ramping voltage with a first increment for each ramping step to read the first plurality of cells, counting, among the first plurality of cells at each ramping step, a first number of logic 1 cells, comparing the first number with a threshold at each ramping step of the first ramping voltage, determining a first voltage reached by the first ramping voltage, at the first voltage the first number becoming equal to or higher than the threshold for the first time, applying a second voltage lower than the first voltage to read the second plurality of cells, and applying a second ramping voltage ramping up from the second voltage with a second predetermined increment lower than the first predetermined increment for each ramping step to read the second plurality of cells.

    Memory cell read operation techniques
    176.
    发明授权
    Memory cell read operation techniques 有权

    公开(公告)号：US12094533B2

    公开(公告)日：2024-09-17

    申请号：US17877613

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Francesco Mastroianni ,  Ferdinando Bedeschi ,  Nevil N. Gajera

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C2013/0057

    Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.

    MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA
    177.
    发明公开
    MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA 审中-公开

    公开(公告)号：US20240232095A9

    公开(公告)日：2024-07-11

    申请号：US17972493

    申请日：2022-10-24

    Applicant: Micron Technology, Inc.

    Inventor： Christophe Vincent Antoine Laurent ,  Ferdinando Bedeschi

    IPC: G06F12/0891

    CPC classification number: G06F12/0891 ,  G06F2212/305

    Abstract: Systems, methods, and apparatus for a memory device that stores a scrub list in a cache used to reduce data traffic to and from a memory array. In one approach, the cache merges the scrub list with cache data. Data in the scrub list can be identified and distinguished from the cache data by adding a one-bit scrub flag to each data entry in the merged cache. In this merged approach, the cache data shares the same memory as the scrub list. Read data that has an error is saved temporarily in this merged cache until the correct value for the data is written back into the memory array.

    Transistor configurations for vertical memory arrays
    179.
    发明授权
    Transistor configurations for vertical memory arrays 有权

    公开(公告)号：US11989427B2

    公开(公告)日：2024-05-21

    申请号：US17823371

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

    Abstract: Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS
    180.
    发明公开
    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS 审中-公开

    公开(公告)号：US20240134533A1

    公开(公告)日：2024-04-25

    申请号：US18396414

    申请日：2023-12-26

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: G06F3/06

    CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0679

    Abstract: A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.

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