中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

409 records (took 0.026 seconds)

    Memory Circuitry And Method Used In Forming Memory Circuitry
    171.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240206175A1

    公开(公告)日：2024-06-20

    申请号：US18540147

    申请日：2023-12-14

    Applicant: Micron Technology, Inc.

    Inventor： Sidhartha Gupta ,  Adam W. Saxler ,  Andrew Li ,  John D. Hopkins

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers directly above a conductor tier. The first tiers comprise sacrificial material and the second tiers comprise non-sacrificial material that is of different composition from that of the sacrificial material. The stack comprises horizontally-elongated trenches extending through the first tiers and the second tiers and are individually between immediately-laterally-adjacent memory-block regions. Channel-material strings are formed that extend through the first and second tiers in the memory-block regions. Through the horizontally-elongated trenches, the sacrificial material is replaced with conductive material that comprises control-gate lines in the memory-block regions. After the replacing, conducting material is formed in a lowest of the first tiers and directly electrically couples together the channel material of the channel-material strings and conductor material of the conductor tier. Other embodiments, including structure, are disclosed.

    Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    172.
    发明公开
    Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 审中-公开

    公开(公告)号：US20240203496A1

    公开(公告)日：2024-06-20

    申请号：US18588407

    申请日：2024-02-27

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42344 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    174.
    发明公开
    Integrated Assemblies and Methods of Forming Integrated Assemblies 审中-公开

    公开(公告)号：US20240164093A1

    公开(公告)日：2024-05-16

    申请号：US18415928

    申请日：2024-01-18

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H10B41/27 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/06 ,  H10B43/27

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

    Microelectronic devices including an interdeck region between deck structures, and related electronic devices
    177.
    发明授权
    Microelectronic devices including an interdeck region between deck structures, and related electronic devices 有权

    公开(公告)号：US11955330B2

    公开(公告)日：2024-04-09

    申请号：US17804978

    申请日：2022-06-01

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Damir Fazil

    IPC: H01L21/02 ,  H01L21/311

    CPC classification number: H01L21/02164 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/02271

    Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

    ELECTRONIC DEVICES COMPRISING BLOCKING REGIONS, AND RELATED ELECTRONIC SYSTEMS AND METHODS
    179.
    发明公开
    ELECTRONIC DEVICES COMPRISING BLOCKING REGIONS, AND RELATED ELECTRONIC SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20240074178A1

    公开(公告)日：2024-02-29

    申请号：US17823276

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L21/28518

    Abstract: An electronic device comprising one or more blocking regions. The electronic device also comprises a source stack comprising one or more conductive materials, a source contact vertically adjacent to the source stack, and a doped semiconductive material vertically adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are vertically adjacent to the doped semiconductive material, and pillars extend through the tiers of alternating conductive materials and dielectric materials, the doped semiconductive material, and the source contact and into the source stack. The one or more blocking regions are laterally adjacent to the semiconductive material. Additional electronic devices, electronic systems, and methods are also disclosed.

    Microelectronic devices, memory devices, and electronic systems
    180.
    发明授权
    Microelectronic devices, memory devices, and electronic systems 有权

    公开(公告)号：US11917817B2

    公开(公告)日：2024-02-27

    申请号：US17125200

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

    IPC: H10B43/50 ,  H10B41/27 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

Patent Agency Ranking