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公开(公告)号：US10727250B2
公开(公告)日：2020-07-28
申请号：US16430713
申请日：2019-06-04
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , John Mark Meldrim , E. Allen McTeer
IPC: H01L27/11582 , H01L27/11556 , H01L27/11565
Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.
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公开(公告)号：US20200161332A1
公开(公告)日：2020-05-21
申请号：US16751116
申请日：2020-01-23
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Chet E. Carter , Collin Howder , John Mark Meldrim , Everett A. McTeer
IPC: H01L27/11582 , H01L21/28 , H01L27/11556 , H01L23/528 , H01L21/768 , H01L21/285 , H01L23/532 , H01L29/10 , H01L21/3213
Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.
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173.发明申请公开(公告)号：US20190189630A1
公开(公告)日：2019-06-20
申请号：US16186042
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , John Mark Meldrim , Everett A. McTeer
IPC: H01L27/11556
CPC classification number: H01L27/11556 , H01L21/28518 , H01L21/28562 , H01L21/28568 , H01L27/11519 , H01L27/11565 , H01L27/11582
Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.
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公开(公告)号：US10283524B1
公开(公告)日：2019-05-07
申请号：US15848612
申请日：2017-12-20
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Chet E. Carter , Collin Howder , John Mark Meldrim , Everett A. McTeer
IPC: H01L21/28 , H01L29/10 , H01L29/49 , H01L21/285 , H01L21/768 , H01L23/528 , H01L23/532 , H01L21/3213 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.
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公开(公告)号：US20250166704A1
公开(公告)日：2025-05-22
申请号：US19027291
申请日：2025-01-17
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Collin Howder , Jordan D. Greenlee
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises an upper second tier comprising insulative material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion. Channel-material strings are formed that extend through the upper portion to the lower portion. Horizontally-elongated lines are formed in the upper second tier longitudinally-along opposing lateral edges of the memory-block regions. Material of the lines is of different composition from that of the insulative material in the upper second tier that is laterally-between the lines. Horizontally-elongated trenches are formed into the stack that are individually between immediately-laterally-adjacent of the memory-block regions and that extend through the upper portion to the lower portion. Other embodiments, including structure independent of method, are disclosed.
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Patent Agency Ranking
公开(公告)号：US20250159890A1
公开(公告)日：2025-05-15
申请号：US19025791
申请日：2025-01-16
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Rita J. Klein , Jordan D. Greenlee
Abstract: Electronic devices (e.g., semiconductor devices, which may be configured for 3D NAND memory devices), comprise pillars extending through a stack of alternating conductive tiers and insulative tiers. The conductive tiers, which may include control gates for access lines (e.g., word lines), include conductive rails along an outer sidewall of the conductive tiers, distal from the pillars extending through the conductive tiers. The conductive rails protrude laterally beyond outer sidewalls of the insulative tiers. The conductive rails increase the amount of conductive material that may otherwise be in the conductive tiers, which may enable the conductive material to exhibit a lower electrical resistance, improving operational performance of the electronic devices.
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公开(公告)号：US12255143B2
公开(公告)日：2025-03-18
申请号：US17187481
申请日：2021-02-26
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , Jordan D. Greenlee , John D. Hopkins
IPC: H01L23/532 , H01L23/528 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
Abstract: A microelectronic device includes a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulative structures. The staircase structure has steps including edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures includes a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US12250812B2
公开(公告)日：2025-03-11
申请号：US18094906
申请日：2023-01-09
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Nancy M. Lomeli , John D. Hopkins , Jiewei Chen , Indra V. Chary , Jun Fang , Vladimir Samara , Kaiming Luo , Rita J. Klein , Xiao Li , Vinayak Shamanna
Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12171101B2
公开(公告)日：2024-12-17
申请号：US17822708
申请日：2022-08-26
Applicant: Micron Technology, Inc.
Inventor： Daniel Billingsley , Matthew J. King , Jordan D. Greenlee , Yongjun J. Hu , Tom George , Amritesh Rai , Sidhartha Gupta , Kyle A. Ritter
Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
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180.发明公开公开(公告)号：US20240268093A1
公开(公告)日：2024-08-08
申请号：US18435212
申请日：2024-02-07
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Jieun Lee , Andrea Gotti , Kai Yen Lo , David McShannon , Daniel Rave , Silvia Borsari , Hsiao Wei Liu
IPC: H10B12/00
CPC classification number: H10B12/033 , H10B12/315
Abstract: A method used in forming an array of capacitors comprises forming a stack comprising sacrificial material and insulative material that is between a top and a bottom of the sacrificial material. The insulative material at least predominately comprises at least one of a silicon nitride, a silicon boronitride, and a silicon carbonitride. Horizontally-spaced openings are formed partially through the sacrificial material. A lining is deposited within the horizontally-spaced openings and directly above the sacrificial material. After depositing the lining, the horizontally-spaced openings are extended through remaining of the sacrificial material. The extended horizontally-spaced openings extend through the insulative material. The insulative material with extended horizontally-spaced openings there-through comprises an insulative horizontal lattice. First capacitor electrodes are formed that are individually within individual of the extended horizontally-spaced openings laterally over the lining that is in the extended horizontally-spaced openings. The sacrificial material is removed and forms a capacitor insulator over the first capacitor electrodes and the insulative horizontal lattice. Second-capacitor-electrode material is formed over the capacitor insulator. Structure independent of method is disclosed
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