公开(公告)号：US08711849B2

公开(公告)日：2014-04-29

申请号：US12946780

申请日：2010-11-15

Applicant: Kai-Yeung (Sunny) Siu ,  Brian Hang Wai Yang ,  Mizanur M. Rahman

Inventor： Kai-Yeung (Sunny) Siu ,  Brian Hang Wai Yang ,  Mizanur M. Rahman

IPC: H04L12/50 ,  H04Q3/68

CPC classification number: H04Q3/68 ,  H04L12/5601 ,  H04L49/108 ,  H04L49/153 ,  H04L49/60 ,  H04L49/606 ,  H04L2012/5627 ,  H04L2012/5651 ,  H04L2012/5681

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.

Abstract translation: 网络交换机包括用于接收具有一组单元的数据流的输入层。 每个小区包括指定目的地设备的数据和报头。 输入层包括一组输入层电路。 该组输入层电路的选定输入层电路接收数据流。 所选择的输入层电路包括与一组目的地设备相对应的一组队列。 所选择的输入层电路被配置为将所选择的单元从数据流分配给该组队列的选定队列。 所选择的队列对应于由所选小区的头部指定的所选目的地设备。 中间层包括一组中间层电路，每个中间层电路具有与该组目标设备相对应的一组缓冲器。 所述一组中间层电路的所选择的中间层电路接收所选择的单元并将所选择的单元分配给与所选择的目的地设备相对应的选定缓冲器。 输出层包括与目标设备组对应的一组输出层电路。 所述一组输出层电路的所选输出层电路在将所选择的单元路由选定的输出层电路输出节点之前存储所选择的单元。

公开(公告)号：US08660820B2

公开(公告)日：2014-02-25

申请号：US13220505

申请日：2011-08-29

Applicant: Roy G. Batruni

Inventor： Roy G. Batruni

IPC: H04B3/04 ,  H04B3/00 ,  H04B3/06 ,  H04B3/21

CPC classification number: H03F1/3247 ,  H03H21/0012 ,  H03H2021/0083 ,  H03M1/0614 ,  H03M1/1042 ,  H03M1/12

Abstract: An adaptive distortion reduction system comprising: an input interface to receive a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal; and an adaptive distortion reduction module coupled to the input interface, to perform linearization based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component; wherein the adaptive self-linearization module includes: a first digital signal processor (DSP) that is adapted to obtain a filter transfer function that approximates a transfer function to be corrected; and a second DSP that is configured using configuration parameters of the first DSP.

Abstract translation: 一种自适应失真降低系统，包括：输入接口，用于接收包含失真分量和未失真分量的失真信号，所述失真分量至少部分归因于外生信号; 以及耦合到所述输入接口的自适应失真减小模块，以至少部分地基于所述失真信号和与所述外生信号相关联的信息来执行线性化，以获得基本上类似于所述未失真分量的校正信号; 其中所述自适应自线性化模块包括：第一数字信号处理器（DSP），其适于获得近似要校正的传递函数的滤波器传递函数; 以及使用第一DSP的配置参数配置的第二DSP。

公开(公告)号：US08631195B1

公开(公告)日：2014-01-14

申请号：US12132053

申请日：2008-06-03

Applicant: Sandeep Khanna ,  Maheshwaran Srinivasan ,  Mark Birman

Inventor： Sandeep Khanna ,  Maheshwaran Srinivasan ,  Mark Birman

IPC: G06F12/00

CPC classification number: G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: A search system for detecting whether one or more overlapping sequences of input characters match a regular expression including a prefix string preceding an intermediate expression having a quantified number m of characters belonging to a specified character class is disclosed. The search system includes a CAM array for storing the regular expression, a shift register for counting sequences of input characters that match the character class, and a control circuit that enables the shift register in response to a prefix match and increments the shift register in response to character class matches.

Abstract translation: 公开了一种用于检测输入字符的一个或多个重叠序列与包含具有属于指定字符类的字符的量化数字m的中间表达式之前的前缀字符串的正则表达式相匹配的搜索系统。 搜索系统包括用于存储正则表达式的CAM阵列，用于对与字符类匹配的输入字符的序列进行计数的移位寄存器以及响应于前缀匹配使移位寄存器能够响应的递增移位寄存器的控制电路 到角色类比赛。

公开(公告)号：US20130315258A1

公开(公告)日：2013-11-28

申请号：US13925531

申请日：2013-06-24

Applicant: NetLogic Microsystems, Inc.

Inventor： Paolo NARVAEZ ,  Murat Bog

IPC: H04L12/939

CPC classification number: H04L49/552 ,  H04J3/062 ,  H04J3/12 ,  H04J3/1611 ,  H04J3/1617 ,  H04J2203/0069 ,  H04J2203/0085 ,  H04J2203/0094 ,  H04L12/54 ,  H04L49/351

Abstract: A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate desequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to desequencing control commands received from the LCAS control manager.

Abstract translation: 提供了一种用于在网络系统中执行本地中心授权服务（LCAS）的系统和方法，所述系统具有数据对准器，其被配置为根据成员组来对齐输入数据的字节。 该系统还包括LCAS控制管理器，该LCAS控制管理器被配置为响应于从数据对准器输入的数据来生成排序控制命令。 该系统进一步包括解调器，其被配置为根据从LCAS控制管理器接收的预定控制命令来对从数据对准器输入的输入数据进行排序。

公开(公告)号：US08589658B2

公开(公告)日：2013-11-19

申请号：US13330662

申请日：2011-12-19

Applicant: Gaurav Singh ,  Daniel Chen ,  Dave Hass

Inventor： Gaurav Singh ,  Daniel Chen ,  Dave Hass

IPC: G06F12/08

CPC classification number: G06F12/1027 ,  Y02D10/13

Abstract: Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

Abstract translation: 呈现用于将虚拟地址转换成物理地址的扩展翻译后备缓冲器（eTLB），eTLB包括具有多个物理地址的物理存储器地址存储器，虚拟存储器地址存储器，被配置为存储对应的多个虚拟存储器地址 物理地址，虚拟存储器地址存储包括集合关联存储器结构（SAM）和内容可寻址存储器（CAM）结构; 以及用于确定所请求的地址是否存在于所述虚拟存储器地址存储器中的比较电路，其中所述eTLB被配置为接收用于识别所述SAM结构和所述CAM结构的索引寄存器，并且其中所述eTLB被配置为接收用于 提供与所述多个虚拟存储器地址对应的虚拟页码。

公开(公告)号：US08582338B1

公开(公告)日：2013-11-12

申请号：US13149878

申请日：2011-05-31

Applicant: Dimitri Argyres

Inventor： Dimitri Argyres

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: Ternary CAM cells are disclosed that include a compare circuit that includes a discharge path having a single pull-down transistor coupled between the match line and ground potential.

Abstract translation: 公开了三元CAM单元，其包括比较电路，该比较电路包括具有耦合在匹配线和地电位之间的单个下拉晶体管的放电路径。

公开(公告)号：US08549341B2

公开(公告)日：2013-10-01

申请号：US12201689

申请日：2008-08-29

Applicant: Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

Inventor： Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

IPC: G06F1/00

CPC classification number: G06F1/00 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0667 ,  H04J3/0685

Abstract: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

Abstract translation: 提供了一种用于减少与多核，多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心，多个用于网络通信的网络接口，以及定时器电路，用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

公开(公告)号：US08527488B1

公开(公告)日：2013-09-03

申请号：US12832862

申请日：2010-07-08

Applicant: Alexei Starovoitov

Inventor： Alexei Starovoitov

IPC: G06F17/30

CPC classification number: G06F17/30985

Abstract: A content search system determines whether an input string matches a negative regular expression that includes a negative pattern and an optional positive pattern. If the input string matches the positive pattern and does not match the negative pattern, a match between the input string and the negative regular expression is indicated. The positive pattern and the negative pattern may be compared to the input string in a single pass of the input string. The content search system may be implemented in a content addressable memory (CAM) device. The negative regular expression may specify a particular portion of the input string, such as a range of characters or bytes of a data packet, in which the negative pattern should not match for a match between the negative regular expression and the input pattern to be indicated.

Abstract translation: 内容搜索系统确定输入字符串是否匹配包含负模式和可选正模式的负正则表达式。 如果输入字符串与正模式匹配并且与负模式不匹配，则指示输入字符串与负正则表达式之间的匹配。 可以在输入串的单次通过中将正模式和负模式与输入字符串进行比较。 内容搜索系统可以在内容可寻址存储器（CAM）设备中实现。 负正则表达式可以指定输入字符串的特定部分，例如数据分组的字符或字节的范围，其中负模式不应与负正则表达式和要指示的输入模式之间的匹配匹配 。

公开(公告)号：US08499302B2

公开(公告)日：2013-07-30

申请号：US13226384

申请日：2011-09-06

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/46 ,  G06F13/00 ,  G06F15/16 ,  G06F15/167 ,  H04L12/56

CPC classification number: H04L49/15 ,  G06F12/0813

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08462841B2

公开(公告)日：2013-06-11

申请号：US11967690

申请日：2007-12-31

Applicant: Erik Schlanger ,  Brendan Donahe ,  Eric Devolder ,  Rens Ross ,  Sandip Ladhani ,  Eric Swartzendruber

Inventor： Erik Schlanger ,  Brendan Donahe ,  Eric Devolder ,  Rens Ross ,  Sandip Ladhani ,  Eric Swartzendruber

IPC: G06K9/46

CPC classification number: H04N19/423 ,  H04N19/44

Abstract: A video processing device (150) includes a bitstream accelerator module (106) and a video processing engine (108). The bitstream accelerator module (106) has an input for receiving a stream of encoded video data, and an output adapted to be coupled to a memory (112) for storing partially decoded video data. The bitstream accelerator module (106) partially decodes the stream of encoded video data according to a selected one of a plurality of video formats to provide the partially decoded video data. The video processing engine (108) has input adapted to be coupled to the memory (112) for reading the partially decoded video data, and an output for providing decoded video data.