公开(公告)号：US20020096494A1

公开(公告)日：2002-07-25

申请号：US09768523

申请日：2001-01-24

Applicant: ProMOS Technologies Inc.

Inventor： Hungyueh Lu ,  Hong-Long Chang ,  Fang-Fei Liu

IPC: B44C001/22 ,  C23F001/00

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76814

Abstract: A post-cleaning method of a via etching process in the present invention has the steps of: (a) performing a photoresist strip process to remove the photoresist layer; b) performing a dry cleaning process which uses CF4 as the main reactive gas and is operated by dual powers; and (c) performing a water-rinsing process.

Abstract translation: 本发明的通孔蚀刻工艺的后清洗方法具有以下步骤：（a）进行光致抗蚀剂剥离处理以除去光致抗蚀剂层; b）进行使用CF4作为主要反应气体并由双重功率运行的干洗过程; 和（c）进行水冲洗处理。

公开(公告)号：US20020033329A1

公开(公告)日：2002-03-21

申请号：US09725219

申请日：2000-11-29

Applicant: ProMos Technologies Inc.

Inventor： Hsiao-Che Wu

IPC: C23C014/34

CPC classification number: C23C14/564

Abstract: The present invention provides a method using plasma burn-in for maintaining the cleanness within a vacuum chamber of a physical vapor deposition system, thereby reducing particles falling upon a processed wafer. After depositing metal compound films on a specific number of wafers, there will be too many metal compound films accumulated within the vacuum chamber of the physical vapor deposition system and these accumulated films are apt to fall off. The plasma burn-in methods in prior art can not substantially prevent metal compound nodules located on the side surface of a metal target from peeling and thus a more frequent plasma burn-in is required. The present invention discovered through experiments that when the operation pressure of the plasma for plasma burn-in is elevated above 10 mtorr, the distribution of the plasma is ever changed and able to enter the narrow space between the metal target side surface and an inner wall of the vacuum chamber so as to bombard the nodules on the side surface and to deposit a metal film upon the brittle metal compound film within the vacuum chamber for reducing the number of particles falling upon the wafer. In this way the present invention enhances the effect of plasma burn-in, reduces the frequency of plasma burn-in operations and increases the throughput.

Abstract translation: 本发明提供了一种使用等离子体老化来保持物理气相沉积系统的真空室内的清洁度的方法，从而减少落在加工晶片上的颗粒。 在特定数量的晶片上沉积金属化合物膜之后，在物理气相沉积系统的真空室内积聚太多的金属化合物膜，并且这些积聚的膜易于脱落。 现有技术中的等离子体老化方法基本上不能防止位于金属靶的侧表面上的金属化合物结节脱落，因此需要更频繁的等离子体老化。 通过实验发现本发明，当等离子体老化的等离子体的操作压力升高到10mtorr以上时，等离子体的分布变化，能够进入金属靶侧表面和内壁之间的狭窄空间 以便轰击侧表面上的结节，并将金属膜沉积在真空室内的脆性金属化合物膜上，以减少落在晶片上的颗粒数量。 以这种方式，本发明增强了等离子体老化的效果，降低了等离子体老化操作的频率并提高了产量。

公开(公告)号：US20020016035A1

公开(公告)日：2002-02-07

申请号：US09816356

申请日：2001-03-26

Applicant: ProMOS Technologies, Inc.

Inventor： Chao-Chueh Wu ,  Sheng-Fen Chiu ,  Jesse Chung ,  Hsiao-Lei Wang

IPC: H01L021/8242 ,  H01L021/20

CPC classification number: H01L27/1087

Abstract: A method is achieved for making improved deep trench capacitors for DRAM circuits with reduced trench faceting at the wafer edge and improved pad Si3N4 uniformity for increasing process yields. The method utilizes a thicker pad Si3N4 as part of a hard mask used to etch the deep trenches. Then, after forming the deep trench capacitors by a sequence of process steps a shallow trench isolation (STI) is formed. The method utilizes etching shallow trenches in the same thicker pad Si3N4 layer and into the silicon substrate. A second insulating layer is deposited and polished back (CMP) into the pad Si3N4 layer. A key feature is to use a second mask to protect the substrate center while partially etching back the thicker portion of pad Si3N4 layer at the substrate edge inherently resulting from the CMP. This minimizes the nonuniformity of the pad Si3N4 layer to provide a more reliable structure for further processing.

Abstract translation: 实现了一种用于在晶片边缘处制造具有减小的沟槽刻面的DRAM电路的改进的深沟槽电容器的方法，并且改善了焊盘Si3N4均匀性以提高工艺产量。 该方法利用较厚的焊盘Si 3 N 4作为用于蚀刻深沟槽的硬掩模的一部分。 然后，在通过一系列工艺步骤形成深沟槽电容器之后，形成浅沟槽隔离（STI）。 该方法利用在较厚的焊盘Si3N4层中蚀刻浅沟槽并进入硅衬底。 将第二绝缘层沉积并抛光（CMP）到焊盘Si3N4层中。 一个关键特征是使用第二掩模来保护衬底中心，同时部分地蚀刻由固化地由CMP产生的衬底边缘处的衬垫Si3N4层的较厚部分。 这使焊盘Si3N4层的不均匀性最小化，以提供用于进一步处理的更可靠的结构。

公开(公告)号：US6130163A

公开(公告)日：2000-10-10

申请号：US326400

申请日：1999-06-03

Applicant: Champion Yi ,  Ching-feng Tsai ,  Jiun-Fang Wang

Inventor： Champion Yi ,  Ching-feng Tsai ,  Jiun-Fang Wang

IPC: B24B37/04 ,  B24B57/02 ,  H01L21/00

CPC classification number: B24B37/0056 ,  B24B37/04 ,  B24B57/02

Abstract: A method of reducing agglomerated particles in a slurry for use in a chemical mechanical polishing (CMP) machine, the CMP machine also using deionized water, is disclosed. The method comprises the steps of: monitoring the pH of the slurry that is provided to the CMP machine; monitoring the pH of the deionized water that is provided to the CMP machine; and adjusting the pH of the deionized water to be substantially the same as the pH of the slurry.

Abstract translation: 公开了一种在用于化学机械抛光（CMP）机器的浆料中还原附聚颗粒的方法，CMP机器也使用去离子水。 该方法包括以下步骤：监测提供给CMP机器的浆料的pH值; 监测提供给CMP机器的去离子水的pH值; 并且将去离子水的pH调节为与浆料的pH基本相同。

公开(公告)号：US6054397A

公开(公告)日：2000-04-25

申请号：US363306

申请日：1999-07-28

Applicant: Yung-nien Teng

Inventor： Yung-nien Teng

IPC: H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L21/304

CPC classification number: H01L21/31053 ,  H01L21/31051 ,  H01L21/31625 ,  H01L21/76819

Abstract: A method for improving the planarization of a BPSG layer over a semiconductor substrate, where the substrate contains underlying structures, is disclosed. The method comprises the steps of: forming a first borophosphosilicate glass (BPSG) layer over and between the underlying structures; reflowing the first BPSG layer using a thermal process; performing a chemical mechanical polishing (CMP) step on the first BPSG layer; forming a second BPSG layer over the first BPSG layer; and reflowing the second BPSG layer using a thermal process.

Abstract translation: 公开了一种用于改善半导体衬底上的BPSG层的平坦化的方法，其中衬底包含底层结构。 该方法包括以下步骤：在下面的结构之上和之间形成第一硼磷硅酸盐玻璃（BPSG）层; 使用热处理回流第一BPSG层; 在第一BPSG层上进行化学机械抛光（CMP）步骤; 在所述第一BPSG层上形成第二BPSG层; 并使用热处理回流第二BPSG层。

公开(公告)号：US5925576A

公开(公告)日：1999-07-20

申请号：US136704

申请日：1998-08-19

Applicant: Cheng-An Peng

Inventor： Cheng-An Peng

IPC: B24B37/30 ,  B24B49/16 ,  H01L21/00

CPC classification number: B24B37/30 ,  B24B49/16 ,  H01L21/67242

Abstract: A plug for plugging selected perforations in a carrier assembly used in a chemical mechanical polishing system for polishing semiconductor wafers is disclosed. The plug comprises a pressure-resistant portion; a bottom portion attached to the pressure-resistant portion; and a leak-resistant portion extending from the pressure-resistant portion, dimensioned to fit snugly into the bottom portion.

Abstract translation: 公开了用于在用于抛光半导体晶片的化学机械抛光系统中使用的载体组件中插入所选穿孔的插头。 塞子包括耐压部分; 附接到耐压部分的底部; 以及从耐压部分延伸的防漏部分，其尺寸适于紧密地配合到底部。

公开(公告)号：US08305425B2

公开(公告)日：2012-11-06

申请号：US12545296

申请日：2009-08-21

Applicant: Mei Len ,  Chin-Hai Chang

Inventor： Mei Len ,  Chin-Hai Chang

IPC: H04N7/00 ,  G02B13/06

CPC classification number: G02B13/06 ,  G03B37/00 ,  H04N5/2254 ,  H04N5/2259 ,  H04N5/23238

Abstract: A panoramic camera system is disclosed that includes an unified optical system, an image capture device, and a processing unit. The unified optical system may include a first set of lenses that guide images received from horizontal directions of a target scene that surrounds the unified optical system. The unified optical system may also include a deflecting device that deflects the images guided through the first set of lenses and a second set of lenses that projects the images deflected by the deflecting device. The image capture device collects the projected images into a determined pattern based on the second set of lenses. Moreover, the processing unit processes the collected images from the image capture device to generate at least one of image signals and video signals representing a panoramic rendition of the target scene.

Abstract translation: 公开了一种全景相机系统，其包括统一的光学系统，图像捕获装置和处理单元。 统一的光学系统可以包括引导从包围统一光学系统的目标场景的水平方向接收的图像的第一组透镜。 统一的光学系统还可以包括偏转装置，该偏转装置偏转引导穿过第一组透镜的图像和投影由偏转装置偏转的图像的第二组透镜。 图像捕获装置基于第二组透镜将投影图像收集成确定的图案。 此外，处理单元处理从图像捕获装置收集的图像，以产生表示目标场景的全景再现的图像信号和视频信号中的至少一个。

公开(公告)号：US08216877B2

公开(公告)日：2012-07-10

申请号：US13079840

申请日：2011-04-05

Applicant: Yen Chuo ,  Hong-Hui Hsu

Inventor： Yen Chuo ,  Hong-Hui Hsu

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract translation: 提供了相变存储器。 相变存储器包括衬底。 在基板上形成第一电极。 圆形或线性相变层电连接到第一电极。 形成在所述相变层上并与所述相变层电连接的第二电极，其中所述第一电极和所述第二电极中的至少一个包括相变材料。

公开(公告)号：US08071970B2

公开(公告)日：2011-12-06

申请号：US12328745

申请日：2008-12-04

Applicant: Chien-Min Lee

Inventor： Chien-Min Lee

IPC: H01L47/00

CPC classification number: H01L45/1675 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or the phase change layer is disclosed.

Abstract translation: 一种相变存储器件，包括电极，在其交叉区域交叉并接触电极的相变层和包括源极和漏极的晶体管，其中晶体管的漏极电连接电极或相变层是 披露

公开(公告)号：US07919384B2

公开(公告)日：2011-04-05

申请号：US12050649

申请日：2008-03-18

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L21/20

CPC classification number: H01L28/91

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract translation: 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。