公开(公告)号：US20240004721A1

公开(公告)日：2024-01-04

申请号：US17853294

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Alexander J. Branover ,  Benjamin Tsien ,  Elliot H. Mednick

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038 ,  G06F9/5033 ,  G06F9/5016

Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.

公开(公告)号：US20240004657A1

公开(公告)日：2024-01-04

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20240004656A1

公开(公告)日：2024-01-04

申请号：US17853790

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Elliott David Binder ,  Onur Kayiran ,  Masab Ahmad

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3851 ,  G06F9/3887

Abstract: Methods and systems are disclosed for processing a vector by a vector processor. Techniques disclosed include receiving predicated instructions by a scheduler, each of which is associated with an opcode, a vector of elements, and a predicate. The techniques further include executing the predicated instructions. Executing a predicated instruction includes compressing, based on an index derived from a predicate of the instruction, elements in a vector of the instruction, where the elements in the vector are contiguously mapped, then, after the mapped elements are processed, decompressing the processed mapped elements, where the processed mapped elements are reverse mapped based on the index.

公开(公告)号：US20240004448A1

公开(公告)日：2024-01-04

申请号：US17853759

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Eric D. Meyer ,  Austin Hung ,  Tianshu Liu

IPC: G06F1/28 ,  G06F11/30

CPC classification number: G06F1/28 ,  G06F11/3062

Abstract: Systems, apparatuses, and methods for dynamically estimating power losses in a computing system. A system management circuit tracks a state of a computing system and dynamically estimates power losses in the computing system based in part on the state. Based on the estimated power losses, power consumption of the computing system is estimated. In response to detecting reduced power losses in at least a portion of the computing system, the system management circuit is configured to increase a power-performance state of one or more circuits of the computing system while remaining within a power allocation limit of the computing system.

公开(公告)号：US11860755B2

公开(公告)日：2024-01-02

申请号：US17861435

申请日：2022-07-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Jinyoung Choi

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/07 ,  G06F11/34

CPC classification number: G06F11/3037 ,  G06F11/076 ,  G06F11/3471 ,  G06F11/3476

Abstract: An approach is provided for implementing memory profiling aggregation. A hardware aggregator provides memory profiling aggregation by controlling the execution of a plurality of hardware profilers that monitor memory performance in a system. For each hardware profiler of the plurality of hardware profilers, a hardware counter value is compared to a threshold value. When a threshold value is satisfied, execution of a respective hardware profiler of the plurality of hardware profilers is initiated to monitor memory performance. Multiple hardware profilers of the plurality of hardware profilers may execute concurrently and each generate a result counter value. The result counter values generated by each hardware profiler of the plurality of hardware profilers are aggregated to generate an aggregate result counter value. The aggregate result counter value is stored in memory that is accessible by a software processes for use in optimizing memory-management policy decisions.

公开(公告)号：US20230420036A1

公开(公告)日：2023-12-28

申请号：US18240770

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriseshan Srikanth ,  Vignesh Adhinarayanan ,  Jagadish B. Kotra ,  Sergey Blagodurov

IPC: G11C11/4093 ,  G11C8/18 ,  H03K19/17728 ,  G11C11/4096 ,  H03K19/173 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C8/18 ,  H03K19/17728 ,  G11C11/4096 ,  H03K19/1737 ,  G11C11/4087

Abstract: A fine-grained dynamic random-access memory (DRAM) includes a first memory bank, a second memory bank, and a dual mode I/O circuit. The first memory bank includes a memory array divided into a plurality of grains, each grain including a row buffer and input/output (I/O) circuitry. The dual-mode I/O circuit is coupled to the I/O circuitry of each grain in the first memory bank, and operates in a first mode in which commands having a first data width are routed to and fulfilled individually at each grain, and a second mode in which commands having a second data width different from the first data width are fulfilled by at least two of the grains in parallel.

公开(公告)号：US11854652B2

公开(公告)日：2023-12-26

申请号：US17984796

申请日：2022-11-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  Ryan T. Freese ,  Eric W. Busta

IPC: G11C7/06

CPC classification number: G11C7/065

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

公开(公告)号：US20230409868A1

公开(公告)日：2023-12-21

申请号：US17844204

申请日：2022-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Hai Xiao ,  Adam H Li ,  Harris Eleftherios Gasparakis

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/08

Abstract: Activation scaled clipping layers for neural networks are described. An activation scaled clipping layer processes an output of a neuron in a neural network using a scaling parameter and a clipping parameter. The scaling parameter defines how numerical values are amplified relative to zero. The clipping parameter specifies a numerical threshold that causes the neuron output to be expressed as a value defined by the numerical threshold if the neuron output satisfies the numerical threshold. In some implementations, the scaling parameter is linear and treats numbers within a numerical range as being equivalent, such that any number in the range is scaled by a defined magnitude, regardless of value. Alternatively, the scaling parameter is nonlinear, which causes the activation scaled clipping layer to amplify numbers within a range by different magnitudes. Each scaling and clipping parameter is learnable during training of a machine learning model implementing the neural network.

公开(公告)号：US11847055B2

公开(公告)日：2023-12-19

申请号：US17364854

申请日：2021-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/02 ,  G06F12/0862 ,  G06F12/0811

CPC classification number: G06F12/084 ,  G06F12/0238 ,  G06F12/0811 ,  G06F12/0862

Abstract: A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.

公开(公告)号：US11837588B2

公开(公告)日：2023-12-05

申请号：US17978389

申请日：2022-11-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34 ,  H05K3/28

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/49838 ,  H05K1/0231 ,  H05K3/284 ,  H05K3/303 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10636

Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.