公开(公告)号：US20120241846A1

公开(公告)日：2012-09-27

申请号：US13235425

申请日：2011-09-18

申请人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US20120026775A1

公开(公告)日：2012-02-02

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C17/12

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US07737041B2

公开(公告)日：2010-06-15

申请号：US12059280

申请日：2008-03-31

申请人： Masaru Kito ,  Hideaki Aochi ,  Takayuki Okamura

发明人： Masaru Kito ,  Hideaki Aochi ,  Takayuki Okamura

IPC分类号： H01L21/302

CPC分类号： H01L21/3086 ,  H01L21/3088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11524

摘要： A semiconductor device comprises a semiconductor layer including a plurality of paralleled linear straight sections extending in a first direction. The layer also includes a plurality of connecting sections each having a width in the first direction sufficient to form a wire-connectable contact therein and arranged to connect between adjacent ones of the straight sections in a second direction. The connecting sections have respective ends formed aligned with a first straight line parallel to the second direction.

摘要翻译： 半导体器件包括半导体层，该半导体层包括在第一方向上延伸的多个平行的线性直线部分。 该层还包括多个连接部分，每个连接部分具有在第一方向上的宽度，足以在其中形成可接线的触点，并且布置成在第二方向上在相邻的直部分之间连接。 连接部具有与平行于第二方向的第一直线对准的各自的端部。

公开(公告)号：US07084450B2

公开(公告)日：2006-08-01

申请号：US10806398

申请日：2004-03-23

申请人： Masaru Kito ,  Hideaki Aochi

发明人： Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10867 ,  H01L27/10829

摘要： A semiconductor memory device includes an element region and an element-isolating region provided on a semiconductor substrate, a capacitor formed in a trench, a first insulating film formed on a side surface of the trench on the capacitor, a first conductive layer provided on the first insulating film and the capacitor so as to bury the trench, a second insulating film provided on a side surface of the trench and on the first insulating film and on both side surfaces of the element region, a gate electrode provided on the element region through a gate insulating film, a source region and a drain region provided in the element region, and a contact layer provided on the first conductive layer and the element region to connect the first conductive layer with the source region or the drain region.

摘要翻译： 半导体存储器件包括元件区域和设置在半导体衬底上的元件隔离区域，形成在沟槽中的电容器，形成在电容器上的沟槽的侧表面上的第一绝缘膜，设置在电容器上的第一导电层 第一绝缘膜和电容器，以埋入沟槽;第二绝缘膜，设置在沟槽的侧表面上，在第一绝缘膜上以及元件区域的两个侧表面上;栅电极，设置在元件区域上，通过 栅极绝缘膜，设置在元件区域中的源极区域和漏极区域，以及设置在第一导电层和元件区域上以将第一导电层与源极区域或漏极区域连接的接触层。

公开(公告)号：US09064975B2

公开(公告)日：2015-06-23

申请号：US13409652

申请日：2012-03-01

申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

IPC分类号： H01L29/765 ,  H01L21/84 ,  H01L27/10 ,  H01L27/115 ,  H01L27/12 ,  G11C19/00

CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

公开(公告)号：US20120195128A1

公开(公告)日：2012-08-02

申请号：US13177719

申请日：2011-07-07

申请人： Tomoko FUJIWARA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

发明人： Tomoko FUJIWARA ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC分类号： G11C16/10

CPC分类号： H01L27/11573 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11582 ,  H01L29/792

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure, a semiconductor pillar, a storage layer, an inner insulating film, an outer insulating film, a memory cell transistor. The control unit performs control of setting the thresholds of the memory transistor to either positive or negative, and performs control so that, with one of the thresholds most distant from 0 volts being defined as n-th threshold, width of distribution of m-th threshold (m being an integer of 1 or more smaller than n) having a sign being same as the n-th threshold is set narrower than width of distribution of the n-th threshold.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储器单元和控制单元。 存储单元包括多层结构，半导体柱，存储层，内绝缘膜，外绝缘膜，存储单元晶体管。 控制单元执行将存储晶体管的阈值设置为正或负的控制，并进行控制，使得在距离最远的0V的阈值中的一个被定义为第n阈值时，第m行的分布宽度 具有与第n个阈值相同的符号的阈值（m为小于n的1以上的整数）被设定为窄于第n阈值的分布宽度。

公开(公告)号：US20120181602A1

公开(公告)日：2012-07-19

申请号：US13346888

申请日：2012-01-10

申请人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

发明人： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Kiyotaka Miyano ,  Shinji Mori ,  Ichiro Mizushima

IPC分类号： H01L27/105 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L27/0688 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1207

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion.The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，存储单元阵列部分，单晶半导体层和电路部分。 存储单元阵列部分形成在半导体衬底上，并且包括存储单元。 半导体层形成在存储单元阵列部分上，并且通过形成在延伸穿过存储单元阵列部分的孔中而连接到半导体衬底。 电路部分形成在半导体层上。 半导体层的下部的Ge浓度高于半导体层的上部的Ge浓度。

公开(公告)号：US07118956B2

公开(公告)日：2006-10-10

申请号：US11143441

申请日：2005-06-03

申请人： Masaru Kito ,  Hideaki Aochi

发明人： Masaru Kito ,  Hideaki Aochi

IPC分类号： H01L21/8242 ,  H01L21/331

CPC分类号： H01L27/10867 ,  H01L29/945

摘要： A trench capacitor comprises a semiconductor substrate, a trench, formed in the semiconductor substrate, having upper and lower portions, a first doped polysilicon layer filled in the lower portion through a first dielectric film and doped with a first impurity having a first conductivity type, at least a second doped polysilicon layer filled in the upper portion through a second dielectric film and doped with a second impurity different from the first impurity, the second impurity having the first conductivity type, and a buried strap layer provided on the second doped polysilicon layer and composed of the first doped polysilicon layer.

摘要翻译： 沟槽电容器包括形成在半导体衬底中的半导体衬底，沟槽，具有上部和下部，通过第一电介质膜填充在下部的第一掺杂多晶硅层，并掺杂有具有第一导电类型的第一杂质， 至少第二掺杂多晶硅层，其通过第二电介质膜填充在上部，并且掺杂有不同于第一杂质的第二杂质，第二杂质具有第一导电类型，以及设置在第二掺杂多晶硅层上的掩埋带层 并由第一掺杂多晶硅层组成。

公开(公告)号：US07838996B2

公开(公告)日：2010-11-23

申请号：US11826709

申请日：2007-07-18

申请人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

发明人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.

摘要翻译： 半导体器件包括布线层。 布线层通过沿着硬掩模的侧壁形成具有闭环的侧壁膜，蚀刻出硬掩模以离开侧壁膜，然后用侧壁膜的掩模蚀刻待蚀刻的目标材料来提供 。 布线层包括沿着硬掩模的端部形成的折叠布线部分和由折叠的布线部分连续的两条平行的线构成的平行部分。 布线层具有除了折叠布线部分和平行部分之外的部分中的闭环切割。 折叠的布线部分和平行部分用作用于连接到另一导线的接触区域。

公开(公告)号：US20080017996A1

公开(公告)日：2008-01-24

申请号：US11826709

申请日：2007-07-18

申请人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

发明人： Mitsuru Sato ,  Masaru Kito ,  Yuzo Nagata

IPC分类号： H01L23/482

CPC分类号： H01L21/76838 ,  H01L21/0337 ,  H01L21/32139 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11565 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a wiring layer. The wiring layer is provided by forming a sidewall film having a closed-loop along a sidewall of a hard mask, etching off the hard mask to leave the sidewall film, and then etching a target material to be etched with a mask of the sidewall film. The wiring layer includes a folded wiring section formed along an end of the hard mask, and a parallel section composed of two parallel wires continued from the folded wiring section. The wiring layer has a closed-loop cut made in a portion except for the folded wiring section and the parallel section. The folded wiring section and the parallel section are used as a contact region for connection to another wire.

摘要翻译： 半导体器件包括布线层。 布线层通过沿着硬掩模的侧壁形成具有闭环的侧壁膜，蚀刻出硬掩模以离开侧壁膜，然后用侧壁膜的掩模蚀刻待蚀刻的目标材料来提供 。 布线层包括沿着硬掩模的端部形成的折叠布线部分和由折叠的布线部分连续的两条平行的线构成的平行部分。 布线层具有除了折叠布线部分和平行部分之外的部分中的闭环切割。 折叠的布线部分和平行部分用作用于连接到另一导线的接触区域。