公开(公告)号：US20120049196A1

公开(公告)日：2012-03-01

申请号：US13290275

申请日：2011-11-07

Applicant: James Pan ,  John Pellerin

Inventor： James Pan ,  John Pellerin

IPC: H01L29/786 ,  H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28088 ,  H01L21/28238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.

Abstract translation: 半导体器件在栅极电介质层上具有衬底，栅极电介质层和金属栅电极。 栅极电介质层包括介电常数（k）大于4的氧化物层，并且硅集中在氧化物层与衬底和金属栅电极的界面处。 一种制造半导体器件的方法包括在衬底上形成可移除栅极，在可移除栅极和衬底之间具有栅极电介质层，在衬底上形成电介质层并露出可移除栅极的上表面，去除可移除栅极离开 在电介质层中形成开口，在栅极电介质层上形成保护层并衬套开口，并在开口中形成金属栅电极。 保护层在栅极电介质层和金属栅电极之间具有渐变组成。

公开(公告)号：US07994573B2

公开(公告)日：2011-08-09

申请号：US12334393

申请日：2008-12-12

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.

Abstract translation: 场效应晶体管（FET）包括在第二导电类型的半导体区域上的第一导电类型的体区。 体区与半导体区形成p-n结。 第二导电类型的源区域在身体区域上延伸。 源极区域与身体区域形成p-n结。 栅电极通过栅极电介质相邻延伸而与体区绝缘。 含碳区域在身体区域下方的半导体区域中延伸。

公开(公告)号：US07932556B2

公开(公告)日：2011-04-26

申请号：US12333597

申请日：2008-12-12

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/66

CPC classification number: H01L29/7802 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. Source regions of the second conductivity type extend over the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric layer. Contact openings extend into the body regions between adjacent gate electrodes. A seed layer extends along the bottom of each contact opening. The seed layer serves as a nucleation site for promoting growth of conductive fill material. A conductive fill material fills a lower portion of each contact opening. An interconnect layer fills an upper portion of each contact opening and is in direct contact with the conductive fill material. The interconnect layer is also in direct contact with corresponding source regions along upper sidewalls of the contact openings.

Abstract translation: 场效应晶体管（FET）包括在第二导电类型的半导体区域上的第一导电类型的体区。 第二导电类型的源区域在身体区域上延伸。 栅电极通过栅极介电层相邻延伸而与体区绝缘。 接触开口延伸到相邻栅电极之间的主体区域。 种子层沿着每个接触开口的底部延伸。 种子层用作促进导电填充材料生长的成核位点。 导电填充材料填充每个接触开口的下部。 互连层填充每个接触开口的上部并与导电填充材料直接接触。 互连层也沿着接触开口的上侧壁的相应源极区直接接触。

公开(公告)号：US20110012174A1

公开(公告)日：2011-01-20

申请号：US12891616

申请日：2010-09-27

Applicant: James Pan ,  Qi Wang

Inventor： James Pan ,  Qi Wang

IPC: H01L29/06 ,  H01L21/335

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

Abstract: A trench-gate field effect transistor includes trenches extending into a silicon region of a first conductivity type, and a gate electrodes in each trench. Body regions of second conductivity type extend over the silicon region between adjacent trenches. Each body region forms a PN junction with the silicon region. A gate dielectric layer lines at least upper sidewalls of each trench, and insulates the gate electrode from the body region. Source regions of the first conductivity flank the trenches. A silicon-germanium region vertically extends through each source region and through a corresponding body region, and terminates within the corresponding body region before reaching the PN junction.

Abstract translation: 沟槽栅场效应晶体管包括延伸到第一导电类型的硅区域的沟槽和每个沟槽中的栅电极。 第二导电类型的主体区域延伸在相邻沟槽之间的硅区域上。 每个体区与硅区形成PN结。 栅极电介质层至少在每个沟槽的上侧壁布线，并且使栅电极与身体区域绝缘​​。 第一导电体的源区在沟槽的侧面。 硅 - 锗区域垂直延伸穿过每个源极区域并穿过对应的主体区域，并且在到达PN结点之前终止于相应的体区域内。

公开(公告)号：US07807576B2

公开(公告)日：2010-10-05

申请号：US12143510

申请日：2008-06-20

Applicant: James Pan

Inventor： James Pan

IPC: H01L21/311

CPC classification number: H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/8725

Abstract: A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD.

Abstract translation: 包括沟槽栅极FET的半导体结构如下形成。 使用掩模在半导体区域中形成多个沟槽。 掩模包括（i）半导体区域的表面上的第一绝缘层，（ii）第一绝缘层上的第一氧化阻挡层，以及（iii）第一氧化阻挡层上的第二绝缘层。 沿每个沟槽的底部形成厚底部电介质（TBD）。 第一氧化阻挡层防止在形成TBD期间沿着半导体区域的表面形成电介质层。

公开(公告)号：US20100238743A1

公开(公告)日：2010-09-23

申请号：US12408721

申请日：2009-03-23

Applicant: James Pan

Inventor： James Pan

IPC: G11C7/00

CPC classification number: G11C11/39 ,  H01L27/1027 ,  H01L27/105

Abstract: This disclosure describes a new semiconductor non-volatile memory that can be potentially faster than DRAM and FLASH, and the manufacturing cost can be lower than SRAM, which is volatile. It is possible to fabricate an ULSI microprocessor and this type of new memory array in the same chip—realizing the “embedded” process. There are a CMOS transistor and latched-up Bipolar transistors (A thyristor) in the device. The fast read, write and erase operations are done by charging the MOS gate capacitor interface and sensing the latch-up voltage of the thyristor. The latch-up voltage of the thyristor is reduced for the additional MOSFET current during the write process, causing early avalanche breakdown and the latch-up of the bipolar transistors. The semiconductor memory can be fabricated as a planar device or a vertical device.

Abstract translation: 本公开描述了一种新的半导体非易失性存储器，其可能比DRAM和闪存可能更快，并且制造成本可以低于易失性的SRAM。 可以在相同的芯片中制造ULSI微处理器和这种类型的新存储器阵列，实现“嵌入式”过程。 器件中存在CMOS晶体管和锁存双极晶体管（A晶闸管）。 快速读，写和擦除操作是通过对MOS栅极电容接口充电并感测晶闸管的锁存电压完成的。 在写入过程中，晶闸管的闩锁电压会降低额外的MOSFET电流，从而导致早期的雪崩击穿和双极晶体管的闭锁。 半导体存储器可以被制造为平面器件或垂直器件。

公开(公告)号：US20100028343A1

公开(公告)日：2010-02-04

申请号：US12549497

申请日：2009-08-28

Applicant: Jian Chen ,  Ellen Filvaroff ,  Sherman Fong ,  Dorothy French ,  Audrey Goddard ,  Paul J. Godowski ,  J. Christopher Grimaldi ,  Austin L. Gurney ,  Kenneth J. Hillan ,  Sarah G. Hymowitz ,  Hanzhong Li ,  James Pan ,  Melissa A. Starovasnik ,  Daniel Tumas ,  Menno Van Lookeren ,  Richard Vandlen ,  Colin K. Watanabe ,  P. Mickey Williams ,  William I. Wood ,  Daniel G. Yansura

Inventor： Jian Chen ,  Ellen Filvaroff ,  Sherman Fong ,  Dorothy French ,  Audrey Goddard ,  Paul J. Godowski ,  J. Christopher Grimaldi ,  Austin L. Gurney ,  Kenneth J. Hillan ,  Sarah G. Hymowitz ,  Hanzhong Li ,  James Pan ,  Melissa A. Starovasnik ,  Daniel Tumas ,  Menno Van Lookeren ,  Richard Vandlen ,  Colin K. Watanabe ,  P. Mickey Williams ,  William I. Wood ,  Daniel G. Yansura

IPC: A61K39/395 ,  A61P19/02

CPC classification number: C07K16/244 ,  A61K38/00 ,  C07H21/04 ,  C07K14/54 ,  C07K14/7155 ,  C07K2317/21 ,  C07K2317/24 ,  C07K2317/35 ,  C07K2317/54 ,  C07K2317/55 ,  C07K2317/62 ,  G01N33/505 ,  G01N33/564 ,  G01N33/574 ,  G01N33/57407 ,  G01N33/57423 ,  G01N33/57438 ,  G01N33/57492 ,  G01N2333/54 ,  G01N2333/7155

Abstract: The present invention is directed to novel polypeptides having sequence identity with IL-17, IL-17 receptors and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention. Further provided herein are methods for treating degenerative cartilaginous disorders and other inflammatory diseases.

Abstract translation: 本发明涉及与IL-17，IL-17受体和编码那些多肽的核酸分子具有序列同一性的新型多肽。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。 本文还提供了治疗退行性软骨疾病和其它炎性疾病的方法。

公开(公告)号：US20090318672A1

公开(公告)日：2009-12-24

申请号：US12319421

申请日：2009-01-06

Applicant: Kevin P. Baker ,  Jian Chen ,  Luc Desnoyers ,  Audrey Goddard ,  Paul J. Godowski ,  Austin L. Gurney ,  James Pan ,  Victoria Smith ,  Colin K. Watanabe ,  William I. Wood ,  Zemin Zhang

Inventor： Kevin P. Baker ,  Jian Chen ,  Luc Desnoyers ,  Audrey Goddard ,  Paul J. Godowski ,  Austin L. Gurney ,  James Pan ,  Victoria Smith ,  Colin K. Watanabe ,  William I. Wood ,  Zemin Zhang

IPC: C07K16/18

CPC classification number: C07K14/47 ,  A01K2217/075 ,  A01K2227/105 ,  A61K38/00 ,  C07K14/4748 ,  C07K14/705 ,  C07K14/82 ,  C07K16/28 ,  C07K2319/30 ,  C12Q1/6816 ,  C12Q1/6883 ,  C12Q1/6886 ,  C12Q2600/136 ,  C12Q2600/158 ,  G01N33/5082 ,  G01N33/5308 ,  G01N33/574 ,  G01N33/57419 ,  G01N33/57423 ,  G01N33/57434 ,  G01N33/57484 ,  G01N33/57488 ,  G01N33/57492 ,  G01N2500/00 ,  C12Q2563/131 ,  C12Q2527/137

Abstract: The present invention is directed to novel polypeptides and to nucleic acid molecules encoding those polypeptides. Also provided herein are vectors and host cells comprising those nucleic acid sequences, chimeric polypeptide molecules comprising the polypeptides of the present invention fused to heterologous polypeptide sequences, antibodies which bind to the polypeptides of the present invention and to methods for producing the polypeptides of the present invention.

Abstract translation: 本发明涉及新型多肽和编码那些多肽的核酸分子。 本文还提供了包含那些核酸序列的载体和宿主细胞，包含与异源多肽序列融合的本发明的多肽的嵌合多肽分子，与本发明的多肽结合的抗体以及本发明的多肽的制备方法 发明。

公开(公告)号：US20090302381A1

公开(公告)日：2009-12-10

申请号：US12334393

申请日：2008-12-12

Applicant: James Pan

Inventor： James Pan

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/046 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A field effect transistor (FET) includes body regions of a first conductivity type over a semiconductor region of a second conductivity type. The body regions form p-n junctions with the semiconductor region. Source regions of the second conductivity type extend over the body regions. The source regions form p-n junctions with the body regions. Gate electrodes extend adjacent to but are insulated from the body regions by a gate dielectric. A carbon-containing region extends in the semiconductor region below the body regions.

Abstract translation: 场效应晶体管（FET）包括在第二导电类型的半导体区域上的第一导电类型的体区。 体区与半导体区形成p-n结。 第二导电类型的源区域在身体区域上延伸。 源极区域与身体区域形成p-n结。 栅电极通过栅极电介质相邻延伸而与体区绝缘。 含碳区域在身体区域下方的半导体区域中延伸。

公开(公告)号：US07601574B2

公开(公告)日：2009-10-13

申请号：US11552582

申请日：2006-10-25

Applicant: James Pan

Inventor： James Pan

IPC: H01L21/338

CPC classification number: H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

Abstract: Methods are provided for fabricating a stress enhanced MOS transistor. One such method comprises the steps of depositing and patterning a layer of sacrificial material to form a dummy gate electrode and replacing the dummy gate electrode with a stressed gate electrode. After the stressed gate electrode has been formed by a replacement process, a stress liner is deposited overlying the stressed gate electrode.

Abstract translation: 提供了制造应力增强型MOS晶体管的方法。 一种这样的方法包括以下步骤：沉积和图案化牺牲材料层以形成伪栅电极，并用应力栅电极代替伪栅电极。 在通过更换工艺形成应力栅电极之后，将应力衬垫沉积在应力栅极上。