公开(公告)号：US5659796A

公开(公告)日：1997-08-19

申请号：US422072

申请日：1995-04-13

申请人： Gregory M. Thorson ,  Steven L. Scott

发明人： Gregory M. Thorson ,  Steven L. Scott

IPC分类号： H04L12/56 ,  G06F13/00 ,  G06F13/12

CPC分类号： H04L45/12 ,  H04L45/10

摘要： A method optimizes routing in a multiprocessor computer system by defining two types of virtual channels having virtual channel buffers for storing messages communicated between processing element nodes in the multiprocessor computer system. A dateline is associated to each type of virtual channel, and messages are restrained from crossing a dateline on its associated type of virtual channel to avoid deadlock. A cost function is defined which is correlated to imbalances in the utilization of the two types of virtual channels. The unrestrained messages are allocated between the two types of virtual channels to minimize the cost function by defining an initial virtual channel allocation, randomly modifying the virtual channel allocation, and accepting the random modification if the modification decreases the cost function, else accepting the modification based on a probability that slowly decreases during the allocating step.

摘要翻译： 一种方法通过定义具有用于存储在多处理器计算机系统中的处理元件节点之间传送的消息的虚拟通道缓冲器的两种类型的虚拟通道来优化多处理器计算机系统中的路由。 数据线与每种类型的虚拟通道相关联，并且阻止消息跨越其相关联的虚拟通道类型的数据线以避免死锁。 定义了与两种虚拟通​​道的使用中的不平衡相关的成本函数。 在两种类型的虚拟信道之间分配无限制的消息以通过定义初始虚拟信道分配，随机修改虚拟信道分配来最小化成本函数，并且如果修改降低成本函数则接受随机修改，否则接受基于修改的修改 在分配步骤中缓慢降低的概率。

公开(公告)号：US5623685A

公开(公告)日：1997-04-22

申请号：US347953

申请日：1994-12-01

申请人： George W. Leedom ,  William T. Moore

发明人： George W. Leedom ,  William T. Moore

IPC分类号： G06F17/16 ,  G06F9/38 ,  G06F15/78 ,  G06F12/06

CPC分类号： G06F15/8084 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3836

摘要： Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a "chunk") in a vector register is loaded from memory, the entire chunk is marked valid and thus made available for use by subsequent or pending operations. The vector processing apparatus comprises a plurality of vector registers, wherein each vector register holds a plurality of elements. For each of the vector registers, a validity indicator is provided wherein each validity indicator indicates a subset of the elements in the corresponding vector register which are valid. A chunk-validation controller is coupled to the validity indicators operable to adjust a value of the validity indicator in response to a plurality of elements becoming valid. An arithmetic logical functional unit (ALFU) is coupled to the vector registers to execute functions specified by program instructions. A vector register controller is connected to control the vector registers in response to program instructions in order to cause valid elements of a selected vector register to be successively transmitted to said ALFU, so that elements are streamed through said ALFU at a speed that is determined by the availability of valid elements from the vector registers. The ALFU optionally comprises a processor pipeline to hold operand data for operations not yet completed while receiving operands for successive operations. The ALFU also optionally comprises an address pipeline to hold element addresses corresponding to the operands for operations not yet completed while receiving element addresses corresponding to the operands for successive operations.

摘要翻译： 用于在计算机系统上进行向量处理的方法和装置。 由于向量寄存器中的一组元素（称为“块”）的最后一个元素从存储器加载，所以整个块被标记为有效，因此可以被后续或待处理的操作使用。 矢量处理装置包括多个向量寄存器，其中每个向量寄存器保持多个元素。 对于每个向量寄存器，提供有效性指示符，其中每个有效性指示符指示相应向量寄存器中有效的元素的子集。 块验证控制器耦合到有效性指示符，可操作以响应于多个元素变得有效来调整有效性指示符的值。 算术逻辑功能单元（ALFU）耦合到矢量寄存器以执行由程序指令指定的功能。 连接矢量寄存器控制器以响应于程序指令来控制向量寄存器，以便使所选择的向量寄存器的有效元素被连续发送到所述ALFU，使得元素以所述ALFU的速度被流式化，速度由 矢量寄存器中有效元素的可用性。 ALFU可选地包括一个处理器流水线，用于保存操作数据，以便操作尚未完成，同时接收连续操作的操作数。 ALFU还可选地包括地址流水线，用于保存对应于尚未完成的操作的操作数的元件地址，同时接收与用于连续操作的操作数相对应的元件地址。

公开(公告)号：US5592487A

公开(公告)日：1997-01-07

申请号：US407808

申请日：1995-03-20

申请人： Kevin M. Knecht ,  Eric C. Fromm

发明人： Kevin M. Knecht ,  Eric C. Fromm

IPC分类号： H04L25/49 ,  H04J3/24

CPC分类号： H04L25/4906

摘要： A communications protocol having a plurality of signals, wherein the plurality of signals includes data packets, control packets, checksum packets and sync symbols. One of the control packets is transmitted after a sync symbol is transmitted. One of the sync symbols, data packets or checksum packets is transmitted after the control packet is transmitted. One of the sync symbols is transmitted after one of said checksum packets is transmitted and one of the sync symbols or another of the data packets is transmitted after one of the data packets is transmitted.

摘要翻译： 一种具有多个信号的通信协议，其中所述多个信号包括数据分组，控制分组，校验和分组和同步符号。 在发送同步符号之后发送控制分组之一。 在发送控制分组之后发送同步符号，数据分组或校验和分组之一。 在发送所述校验和分组之一之后发送其中一个同步符号，并且在发送数据分组之一之后发送其中一个同步符号或另一个数据分组。

公开(公告)号：US5581705A

公开(公告)日：1996-12-03

申请号：US166443

申请日：1993-12-13

申请人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

发明人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16

CPC分类号： G06F15/17381

摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

摘要翻译： 描述了消息传送设施，其能够在全局可寻址的分布式存储器多处理器中将数据分组从一个处理元件传递到另一处理元件，而不在目标处理元件的存储器中具有明确的目的地地址。 通过定义一个允许一个处理器将包含操作码，地址和参数的消息发送到另一个处理器的操作码约定，消息传递设施可用于完成远程操作。 目的处理器在到达中断之后收到消息后，可以解码操作码，并使用参数地址和数据执行指示的动作。 消息传递设备提供了构建处理器间通信协议的原语。 操作系统通信和消息传递编程模型可以使用消息传递设备来实现。

公开(公告)号：US5467040A

公开(公告)日：1995-11-14

申请号：US98204

申请日：1993-07-28

申请人： Stephen E. Nelson ,  David L. Duxstad ,  Galen C. Flunker

发明人： Stephen E. Nelson ,  David L. Duxstad ,  Galen C. Flunker

IPC分类号： G06F1/10 ,  H03H11/26 ,  H03K1/04

CPC分类号： G06F1/10

摘要： A method of adjusting clock skew for a computer system, wherein the computer system includes a clock generator for generating a clock signal, at least one logic module and a clock distribution network for carrying the clock signal from the clock generator to the logic modules, includes deskewing each of the logic modules and also deskewing the distribution network between the clock generator and the logic modules. Deskewing is performed by measuring a delay for the clock signal between a clock input and a test point on the logic module, comparing the measured delay to a desired delay, calculating an amount of adjustment needed to cause the measure delay to equal a desired delay and programming a skew compensator on the logic module with a calculator to mount adjustment.

摘要翻译： 一种调整计算机系统的时钟偏移的方法，其中计算机系统包括用于产生时钟信号的时钟发生器，至少一个逻辑模块和用于将来自时钟发生器的时钟信号传送到逻辑模块的时钟分配网络，包括 对每个逻辑模块进行歪斜校正，并且还使时钟发生器和逻辑模块之间的分布网络相互歪斜。 通过测量逻辑模块上的时钟输入和测试点之间的时钟信号的延迟来进行偏移校正，将测量的延迟与期望的延迟进行比较，计算使测量延迟等于所需延迟所需的调整量，以及 用计算器对逻辑模块上的偏移补偿器进行编程，以安装调整。

公开(公告)号：US5434995A

公开(公告)日：1995-07-18

申请号：US165265

申请日：1993-12-10

申请人： Steven M. Oberlin ,  Eric C. Fromm

发明人： Steven M. Oberlin ,  Eric C. Fromm

IPC分类号： F02B75/02 ,  G06F9/46 ,  G06F15/16 ,  G06F15/80

CPC分类号： G06F9/52 ,  G06F9/522 ,  F02B2075/027

摘要： A barrier mechanism provides a low-latency method of synchronizing all or some of the processing elements (PEs) in a massively parallel processing system. The barrier mechanism is supported by several physical barrier synchronization circuits, each receiving an input from every PE in the processing system. Each PE has two associated barrier synchronization registers, in which each bit is used as an input to one of several logical barrier synchronization circuits. The hardware supports both a conventional barrier function and an alternative eureka function. Each bit in each of the barrier synchronization registers can be programmed to perform as either barrier or eureka function, and all bits of the registers and each barrier synchronization circuit functions independently. Partitioning among PEs is accomplished by a barrier mask and interrupt register which enables certain of the bits in the barrier synchronization registers to a defined group of PEs. Further partitioning is accomplished by providing bypass points in the physical barrier synchronization circuits to subdivide the physical barrier synchronization circuits into several types of PE barrier partitions of varying size and shape. The barrier mask and interrupt register and the bypass points are used in concert to accomplish flexible and scalable partitions corresponding to user-desired sizes and shapes with a latency several orders of magnitude faster than existing software implementations.

摘要翻译： 屏障机制提供了在大规模并行处理系统中同步全部或一些处理元件（PE）的低等待时间方法。 屏障机制由几个物理屏障同步电路支持，每个物理屏障同步电路接收处理系统中每个PE的输入。 每个PE具有两个相关联的屏障同步寄存器，其中每个位用作多个逻辑屏障同步电路之一的输入。 该硬件支持传统的屏障功能和另一种尤里卡功能。 每个屏障同步寄存器中的每个位可以被编程为执行屏障或尤里卡功能，并且寄存器和每个屏障同步电路的所有位独立地起作用。 PE之间的分区是通过屏蔽掩码和中断寄存器实现的，这使得屏障同步寄存器中的某些位能够定义为一组PE。 通过在物理屏障同步电路中提供旁路点以将物理屏障同步电路细分为具有不同大小和形状的几种类型的PE屏障隔板来实现进一步划分。 屏蔽掩码和中断寄存器和旁路点一起用于完成与用户期望的大小和形状相对应的灵活和可扩展的分区，其延迟比现有软件实现快几个数量级。

公开(公告)号：US5430884A

公开(公告)日：1995-07-04

申请号：US536409

申请日：1990-06-11

申请人： Douglas R. Beard ,  Andrew E. Phelps ,  Michael A. Woodmansee ,  Richard G. Blewett ,  Jeffrey A. Lohman ,  Alexander A. Silbey ,  George A. Spix ,  Frederick J. Simmons ,  Don A. Van Dyke

发明人： Douglas R. Beard ,  Andrew E. Phelps ,  Michael A. Woodmansee ,  Richard G. Blewett ,  Jeffrey A. Lohman ,  Alexander A. Silbey ,  George A. Spix ,  Frederick J. Simmons ,  Don A. Van Dyke

IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F15/16 ,  G06F15/173 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

CPC分类号： G06F9/30087 ,  G06F11/3632 ,  G06F15/17381 ,  G06F15/8076 ,  G06F15/8092 ,  G06F8/433 ,  G06F8/45 ,  G06F9/30021 ,  G06F9/3004 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3846 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3875 ,  G06F9/3885

摘要： The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector processor is comprised of a scalar processor for operating on scalar and logical instructions, including a plurality of independent functional units operably connected to the scalar processor, a vector processor for operating on vector instructions, including a plurality of independent functional units operably connected to the vector processor, and an instruction control mechanism for fetching both the scalar and vector instructions from an instruction cache and controlling the operation of those instructions in both the scalar and vector processor. The instruction control mechanism is designed to enhance the performance of the scalar/vector processor by keeping a multiplicity of pipelines substantially filled with a minimum number of gaps.

摘要翻译： 本发明是一种改进的高性能标量/向量处理器。 在优选实施例中，在多处理器系统中使用标量/向量处理器。 标量/矢量处理器包括用于对标量和逻辑指令进行操作的标量处理器，包括可操作地连接到标量处理器的多个独立功能单元，用于在矢量指令上操作的矢量处理器，包括多个独立的功能单元， 连接到向量处理器，以及指令控制机制，用于从指令高速缓存取出标量和向量指令，并控制标量和向量处理器中的这些指令的操作。 指令控制机制旨在通过保持基本上填充有最小数量的间隙的多个管线来增强标量/向量处理器的性能。

公开(公告)号：US5428803A

公开(公告)日：1995-06-27

申请号：US912964

申请日：1992-07-10

申请人： Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

发明人： Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

IPC分类号： G06F9/38 ,  G06F1/10 ,  G06F12/06 ,  G06F13/16 ,  G06F15/173 ,  G06F3/60

CPC分类号： G06F13/1657 ,  G06F1/10 ,  G06F13/1663 ,  G06F15/17337 ,  G06F15/17381

摘要： A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.

摘要翻译： 统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。 多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。 如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。 共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用 集群。 分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。 处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

公开(公告)号：US5420583A

公开(公告)日：1995-05-30

申请号：US250375

申请日：1994-05-27

申请人： Kevin M. Knecht ,  Eric C. Fromm

发明人： Kevin M. Knecht ,  Eric C. Fromm

IPC分类号： H04L25/49 ,  H03M7/00

CPC分类号： H04L25/4906

摘要： A digital optical serial communication system and encoding method comprises a transmitter responsive to an input of parallel information for parsing the information into 4-bit groups. The 4-bit groups are encoded into 5-bit codes having a 40/60 duty cycle and wherein no more than two consecutive bits are logical 1's or 0's on either end of the 5-bit code. The 5-bit codes are serially transmitted by an optical transmission medium for providing a conduit from the transmitter to a receiver. The receiver receives and decodes the serial information to 4-bit groups. The 4-bit groups are concatenated to form a parallel packet of information suitable for data processing. The encoding/decoding scheme has the advantages of (1) a worst case duty factor of 40/60%; (2) a maximum run of bits without transition equal to five; (3) an easily recaptured framing of packets due to a unique sync symbol; and (4) simple encoding and decoding of packets using combinational logic rather than lookup tables. In addition, data can be continuously sent via a communications protocol.

摘要翻译： 数字光串行通信系统和编码方法包括响应于并行信息的输入的发送器，用于将信息解析成4位组。 4位组被编码为具有40/60占空比的5位代码，并且其中不超过两个连续位是5位代码的任一端的逻辑1或0。 5位代码通过光传输介质串行传输，用于提供从发射机到接收机的导管。 接收器将串行信息接收并解码为4位组。 4位组被级联以形成适合于数据处理的并行信息包。 编码/解码方案具有以下优点：（1）最差情况占空比为40/60％; （2）无过渡等于5的最大位数; （3）由于唯一的同步符号而容易地重新分组分组; 和（4）使用组合逻辑而不是查找表对数据包进行简单的编码和解码。 此外，可以通过通信协议连续发送数据。

公开(公告)号：US5400504A

公开(公告)日：1995-03-28

申请号：US62995

申请日：1993-05-17

申请人： Eugene F. Neumann ,  Melvin C. August ,  Daniel C. Mansur ,  Albert H. Wilson

发明人： Eugene F. Neumann ,  Melvin C. August ,  Daniel C. Mansur ,  Albert H. Wilson

IPC分类号： H01R43/16

CPC分类号： H01R12/523 ,  Y10S439/908 ,  Y10T29/49165 ,  Y10T29/4922

摘要： A completely shielded metallized connector block for use in multiple circuit modules of an electronic device. Electrical communication between the circuit boards is effected by an array of metallic pins which run through the blocks. The metallization on the nonconductive blocks can be held at ground or at a constant potential to increase the shielding between pins as well as maintaining voltage and ground planes at constant levels throughout the modules. The metallization is insulated from the pins and circuit boards by nonconductive bushings inserted in holes in the blocks. In one embodiment, the metallization consists of copper and solder plating and the blocks are constructed of liquid crystal polymer.

摘要翻译： 一种完全屏蔽的金属化连接器块，用于电子设备的多个电路模块。 电路板之间的电气连接通过穿过块的金属引脚阵列来实现。 非导电块上的金属化可以保持在接地或恒定电位，以增加引脚之间的屏蔽，以及将电压和接地层保持在整个模块中的恒定水平。 金属化通过插入块中的孔中的非导电衬套与销和电路板绝缘。 在一个实施例中，金属化由铜和焊料镀层组成，并且块由液晶聚合物构成。