公开(公告)号：US20120295417A1

公开(公告)日：2012-11-22

申请号：US13109567

申请日：2011-05-17

Applicant: Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

Inventor： Thomas N. Adam ,  Katherina E. Babich ,  Stephen W. Bedell ,  Joel P. de Souza ,  Gerald W. Gibson ,  Alexander Reznicek ,  Devendra K. Sadana ,  Seshadri Subbanna

IPC: H01L21/20

CPC classification number: H01L29/66628 ,  H01L21/0237 ,  H01L21/02524 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/78

Abstract: A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed.

Abstract translation: 提供了一种控制外延生长室中不同材料的成核速率（即孵育时间）的方法，其可以有利于高生长速率并且可以与低温生长相容。 通过选择具有给定的天然成核特性的合适的掩蔽材料，通过相对于相同材料膜的单晶生长改变给定材料膜的生长的成核速率，在外延生长室中控制不同材料的成核速率 ，或通过改变掩模层的表面以获得适当的成核特性。 或者，可以通过相对于其后将形成外延半导体材料的其它区域修改半导体衬底的选定区域的表面来实现成核速率控制。

公开(公告)号：US08288217B2

公开(公告)日：2012-10-16

申请号：US12945026

申请日：2010-11-12

Applicant: Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

Inventor： Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Alexander Reznicek ,  Keith Kwong Hon Wong

IPC: H01L21/338

CPC classification number: H01L29/66545 ,  H01L29/1054 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/7843 ,  H01L29/7848

Abstract: A field effect transistor device includes a gate stack portion disposed on a substrate, and a channel region in the substrate having a depth partially defined by the gate stack portion and a silicon region of the substrate, the silicon region having a sloped profile such that a distal regions of the channel region have greater depth than a medial region of the channel region.

Abstract translation: 场效应晶体管器件包括设置在衬底上的栅极堆叠部分和衬底中的沟道区域，其具有由栅极堆叠部分和衬底的硅区域部分地限定的深度，所述硅区域具有倾斜轮廓，使得 沟道区域的远侧区域具有比沟道区域的中间区域更深的深度。

公开(公告)号：US08263468B2

公开(公告)日：2012-09-11

申请号：US12766859

申请日：2010-04-24

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/78696

Abstract: A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.

Abstract translation: 公开了一种用于制造FET器件的方法。 该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。 选择身体为Si，Ge或其合金混合物。 选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。 这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。 该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。 在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

公开(公告)号：US20120205784A1

公开(公告)日：2012-08-16

申请号：US13037944

申请日：2011-03-01

Applicant: Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/02 ,  H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/0262

Abstract: Compressively strained silicon is epitaxially grown directly onto a silicon substrate at low temperature using hydrogen to engineer the strain level. Hydrogen dilution may be varied during such growth to provide a strain gradient.

Abstract translation: 使用氢将压缩应变硅在低温下直接外延生长到硅衬底上以设计应变水平。 在这样的生长过程中氢稀释可以变化以提供应变梯度。

公开(公告)号：US20120156861A1

公开(公告)日：2012-06-21

申请号：US13405760

申请日：2012-02-27

Applicant: Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

Inventor： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC: H01L21/302

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: Methods for removing or reducing the thickness of a material layer remaining at Si-Si interfaces after silicon wafer bonding. The methods include an anneal which is performed at a temperature sufficient to dissolve oxide, yet not melt silicon.

Abstract translation: 在硅晶片接合之后去除或减少残留在Si-Si界面处的材料层的厚度的方法。 所述方法包括在足以溶解氧化物但不熔融硅的温度下进行的退火。

公开(公告)号：US20120037998A1

公开(公告)日：2012-02-16

申请号：US12855738

申请日：2010-08-13

Applicant: Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

Inventor： Stephen W. Bedell ,  Jee H. Kim ,  Siegfried L. Maurer ,  Alexander Reznicek ,  Devendra K. Sadana

IPC: H01L27/092 ,  H01L21/20

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

Abstract: A p-type field effect transistor (PFET) having a compressively stressed channel and an n-type field effect transistor (NFET) having a tensilely stressed channel are formed. In one embodiment, a silicon-germanium alloy is employed as a device layer, and the source and drain regions of the PFET are formed employing embedded germanium-containing regions, and source and drain regions of the NFET are formed employing embedded silicon-containing regions. In another embodiment, a germanium layer is employed as a device layer, and the source and drain regions of the PFET are formed by implanting a Group IIIA element having an atomic radius greater than the atomic radius of germanium into portions of the germanium layer, and source and drain regions of the NFET are formed employing embedded silicon-germanium alloy regions. The compressive stress and the tensile stress enhance the mobility of charge carriers in the PFET and the NFET, respectively.

Abstract translation: 形成具有压应力通道的p型场效应晶体管（PFET）和具有拉伸应力通道的n型场效应晶体管（NFET）。 在一个实施例中，使用硅 - 锗合金作为器件层，并且使用嵌入的含锗区域形成PFET的源极和漏极区域，并且使用嵌入的含硅区域形成NFET的源极和漏极区域 。 在另一个实施例中，锗层用作器件层，PFET的源极和漏极区通过将原子半径大于锗的原子半径的IIIA族元素注入到锗层的部分中而形成， 使用嵌入式硅 - 锗合金区域形成NFET的源极和漏极区域。 压应力和拉伸应力分别提高了PFET和NFET中载流子的迁移率。

公开(公告)号：US20120031476A1

公开(公告)日：2012-02-09

申请号：US12849966

申请日：2010-08-04

Applicant: Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

Inventor： Stephen W. Bedell ,  Harold J. Hovel ,  Daniel A. Inns ,  Jee H. Kim ,  Alexander Reznicek ,  Devendra K. Sadana

IPC: H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/065 ,  H01L31/03765 ,  H01L31/075 ,  H01L31/18 ,  Y02E10/548

Abstract: A photovoltaic device includes a composition modulated semiconductor structure including a p-doped first semiconductor material layer, a first intrinsic compositionally-graded semiconductor material layer, an intrinsic semiconductor material layer, a second intrinsic compositionally-graded semiconductor layer, and an n-doped first semiconductor material layer. The first and second intrinsic compositionally-graded semiconductor material layers include an alloy of a first semiconductor material having a greater band gap width and a second semiconductor material having a smaller band gap with, and the concentration of the second semiconductor material increases toward the intrinsic semiconductor material layer in the first and second compositionally-graded semiconductor material layers. The photovoltaic device provides an open circuit voltage comparable to that of the first semiconductor material, and a short circuit current comparable to that of the second semiconductor material, thereby increasing the efficiency of the photovoltaic device.

Abstract translation: 光伏器件包括组成调制的半导体结构，其包括p掺杂的第一半导体材料层，第一本征成分梯度半导体材料层，本征半导体材料层，第二本征组分梯度半导体层和n掺杂的第一半导体层 半导体材料层。 第一和第二本征成分梯度半导体材料层包括具有较大带隙宽度的第一半导体材料和具有较小带隙的第二半导体材料的合金，并且第二半导体材料的浓度朝向本征半导体 第一和第二组成梯度半导体材料层中的材料层。 光电器件提供与第一半导体材料相当的开路电压，以及与第二半导体材料相当的短路电流，从而提高光伏器件的效率。

公开(公告)号：US08097516B2

公开(公告)日：2012-01-17

申请号：US12169991

申请日：2008-07-09

Applicant: Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

Inventor： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

IPC: H01L21/336

CPC classification number: H01L21/76229

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract translation: 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

公开(公告)号：US07968459B2

公开(公告)日：2011-06-28

申请号：US12128040

申请日：2008-05-28

Applicant: Stephen W. Bedell ,  Joel P. DeSouza ,  Zhibin Ren ,  Alexander Reznicek ,  Devandra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

Inventor： Stephen W. Bedell ,  Joel P. DeSouza ,  Zhibin Ren ,  Alexander Reznicek ,  Devandra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi

IPC: H01L21/44

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (S/D) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（对绝缘体层上的超薄硅中的FET中的源/漏（S / D）区域的潜在问题）的方法， 以及应变S / D区域的植入物诱导的塑性弛豫（对于其中通道应变由嵌入的S / D区域晶格与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入与“分剂量退火中间”（DDAB）方案中的非原位热处理组合，避免了对能够进行热植入的加工的需要。

公开(公告)号：US20100006985A1

公开(公告)日：2010-01-14

申请号：US12170459

申请日：2008-07-10

Applicant: Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

Inventor： Joel P. DeSouza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra Sadana

IPC: H01L29/12 ,  H01L21/20

CPC classification number: H01L21/76245

Abstract: A method is provided for making a silicon-on-insulator substrate. Such method can include epitaxially growing a highly p-type doped silicon-containing layer onto a major surface of an underlying semiconductor region of a substrate. Subsequently, a non-highly p-type doped silicon-containing layer may be epitaxially grown onto a major surface of the p-type highly-doped epitaxial layer to cover the highly p-type doped epitaxial layer. The overlying non-highly p-type doped epitaxial layer can have a dopant concentration substantially lower than the dopant concentration of the highly p-type doped epitaxial layer. The substrate can then be processed to form a buried oxide layer selectively by oxidizing at least portions of the highly p-type doped epitaxial layer covered by the non-highly p-type doped epitaxial layer, the buried oxide layer separating the overlying monocrystalline semiconductor layer from the underlying semiconductor region. Such processing can be performed while simultaneously annealing the non-highly p-type doped epitaxial layer.

Abstract translation: 提供了一种制造绝缘体上硅衬底的方法。 这种方法可以包括将高p型掺杂的含硅层外延生长到衬底的下面的半导体区域的主表面上。 随后，可以在p型高掺杂外延层的主表面上外延生长非高度p型掺杂的含硅层，以覆盖高度p型掺杂的外延层。 上覆非高p型掺杂外延层可以具有基本上低于高p型掺杂外延层的掺杂剂浓度的掺杂剂浓度。 然后可以通过氧化由非高p型掺杂的外延层覆盖的高p型掺杂外延层的至少一部分来选择性地处理衬底以形成掩埋氧化物层，将覆盖的单晶半导体层 从底层半导体区域。 可以在非高p型掺杂外延层同时退火的同时执行这种处理。