Abstract:
An integrated circuit (IC) includes at least one capacitor with metal electrodes. At least one of the electrodes (10 or 30) is formed from at least surface-silicided hemispherical grain silicon or silicon alloy. A fabrication process for obtaining such a capacitor with silicided metal electrodes is also provided.
Abstract:
An integrated circuit is silicided by depositing at least one metal on a silicon-containing region and forming a metal silicide. Residue metal that has not been silicided during the formation of the metal silicide is then removed. The removal of the residue metal involves the conversion of the residue metal to an alloy containing the germanide of said metal with minimal if any adverse affect on the silicide. Next, the alloy is removed, in a manner selective to the silicide, by dissolving the alloy in a chemical solution.
Abstract:
An integrated circuit is silicided by depositing at least one metal on a silicon-containing region and forming a metal silicide. Residue metal that has not been silicided during the formation of the metal silicide is then removed. The removal of the residue metal involves the conversion of the residue metal to an alloy containing the germanide of said metal with minimal if any adverse affect on the silicide. Next, the alloy is removed, in a manner selective to the silicide, by dissolving the alloy in a chemical solution.
Abstract:
A method for forming silicon-germanium in the upper portion of a silicon substrate, including the steps of: depositing a germanium layer doped at a concentration in dopant elements greater than 1019 atoms per cm3 on a silicon substrate; heating to have the germanium diffuse into the silicon substrate to form a doped silicon-germanium layer in the upper portion of the silicon substrate; and eliminating the germanium layer.
Abstract:
The present invention relates to an improved photolithography process particularly suitable for high-resolution optical lithography techniques using the g, h and i lines of the spectrum of mercury and short-wavelength UV, comprising, prior to deposition of the photosensitive resin on the layer of material to be lithographically patterned, the formation of an antireflective porous layer within the said layer to be lithographically patterned and on the surface of the latter.
Abstract:
A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.
Abstract:
A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.
Abstract:
A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
Abstract:
A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.
Abstract:
A process for fabricating a strained layer of silicon or of a silicon/germanium alloy, includes:a) the formation of a layer (2) of silicon or of a silicon/germanium alloy on a layer (1) of a material having a modifiable lattice parameter; andb) the modification of the lattice parameter.