公开(公告)号：US6087199A

公开(公告)日：2000-07-11

申请号：US18737

申请日：1998-02-04

Applicant: H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

Inventor： H. Bernhard Pogge ,  Bijan Davari ,  Johann Greschner ,  Howard L. Kalter

IPC: H01L21/768 ,  H01L21/98 ,  H01L23/13 ,  H01L25/065 ,  H01L29/06 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L25/50 ,  H01L21/76838 ,  H01L23/13 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/83141 ,  H01L2224/97 ,  H01L29/0657 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/3025

Abstract: A method for fabricating an integrated circuit package or arrangement includes providing a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having conversely matching bottom surface topographies to permit self-aligned positioning of the chip on the carrier. Chips are provided such that top faces of neighboring chips lie substantially in planes separated by a distance of greater than 0.0 .mu.m. The carrier is arranged and dimensioned such that the neighboring chips are separated by a gap G or spacing in a range of 1 .mu.m

Abstract translation: 一种用于制造集成电路封装或布置的方法包括提供具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。 设置芯片使得相邻芯片的顶面基本上位于大于0.0μm的距离上的平面中。 载体的布置和尺寸使得相邻的芯片由间隙G分隔开，或间隔在1μm×100μm的范围内。 在顶面和间隙上设有金属互连。 优选地，互连在间隙上具有逐渐的斜率。

公开(公告)号：US5541427A

公开(公告)日：1996-07-30

申请号：US162588

申请日：1993-12-03

Applicant: Barbara A. Chappell ,  Bijan Davari ,  George A. Sai-Halasz ,  Yuan Taur

Inventor： Barbara A. Chappell ,  Bijan Davari ,  George A. Sai-Halasz ,  Yuan Taur

IPC: G11C11/412 ,  H01L27/11 ,  H01L27/108

CPC classification number: G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

Abstract: A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch. A six device SRAM cell comprises a deep isolation trench formed in the substrate; a first latch including two transistors formed of p-type material on a first side of the trench; a second latch including two transistors formed of n-type material on a second side of the trench opposite the first side of the trench, and connection means for electrically cross wiring the transistors of the first latch to the transistors of the second latch. In forming the latch a self-aligned process for separately forming contacts to diffusion regions and gate stacks on the semiconductor substrate is used.

Abstract translation: 存储锁存器，包括在所述衬底上的栅极绝缘层，穿过所述绝缘层形成的浅沟槽和所述衬底中的沟槽以提供器件绝缘; 以及在浅沟槽之间的衬底中的掺杂区域。 掺杂区域定义源和漏极。 栅极堆叠形成在与掺杂区域相邻的氧化物区域上。 在栅极堆叠之间形成平坦化的绝缘体。 在平坦化的绝缘体中提供了开口，用于与掺杂区域和栅极叠层的接触。 导电材料填充开口以形成用于掺杂区域和栅极叠层的触点。 平坦化绝缘体上的图案化的导电材料层连接用于闩锁的布线部分的所述触点中的所选择的一个。 六器件SRAM单元包括形成在衬底中的深隔离沟槽; 第一锁存器，包括在所述沟槽的第一侧上由p型材料形成的两个晶体管; 包括在与沟槽的第一侧相对的沟槽的第二侧上由n型材料形成的两个晶体管的第二锁存器以及用于将第一锁存器的晶体管与第二锁存器的晶体管电交叉布线的连接装置。 在形成锁存器时，使用用于单独形成与半导体衬底上的扩散区域和栅极堆叠的接触的自对准工艺。

公开(公告)号：US4889819A

公开(公告)日：1989-12-26

申请号：US196398

申请日：1988-05-20

Applicant: Bijan Davari ,  Eti Ganin ,  David L. Harame ,  George A. Sai-Halasz

Inventor： Bijan Davari ,  Eti Ganin ,  David L. Harame ,  George A. Sai-Halasz

IPC: H01L21/265

CPC classification number: H01L21/26513 ,  H01L21/26506

Abstract: Shallow junctions of a first conductivity type in a semiconductor of the opposite conductivity type are fabricated by doping the substrate with a dopant of an opposite conductivity type than the first conductivity type to preamorphize portions of the substrate. The dopant of the opposite conductivity type must have a molecular weight that is higher than the molecular weight of the substrate. The substrate is then doped with the dopant of the first conductivity type to form the shallow junctions.

公开(公告)号：US4881105A

公开(公告)日：1989-11-14

申请号：US206148

申请日：1988-06-13

Applicant: Bijan Davari ,  Wei Hwang ,  Nicky C. Lu

Inventor： Bijan Davari ,  Wei Hwang ,  Nicky C. Lu

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7827 ,  H01L21/823885 ,  H01L27/0925 ,  H01L29/66666 ,  H01L29/4236

Abstract: An integrated, self-aligned trench-transistor structure including trench CMOS devices and vertical "strapping transistors" wherein the shallow trench transistors and the strapping trench-transistors are built on top of buried source junctions. A p- epitaxial layer is grown on a substrate and contains an n-well, an n+ source and a p+ source regions. Shallow trenches are disposed in the epitaxial layer and contain n+ polysilicon or metal, such as tungsten, to provide the trench CMOS gates. A gate contact region connects the trenches and the n+ polysilicon or metal in the trenches. The n+ polysilicon or metal in the trenches are isolated by a thin layer of silicon dioxide on the trench walls of the gates. The p+ drain region, along with the filled trench gate element and the p+ source region, form a vertical p-channel (PMOS) trench-transistor. The n+ drain region, along with filled trench gate element and the n+ source form a vertical n-channel (NMOS) transistor. The PMOS and NMOS trench transistors are isolated by shallow trench isolation regions and an oxide layer.

公开(公告)号：US07974826B2

公开(公告)日：2011-07-05

申请号：US11234438

申请日：2005-09-23

Applicant: Bijan Davari ,  Scott Terrell Williams ,  Peter Anton Pechtl ,  Larry Keith McDonald ,  Alfred Ong'iro

Inventor： Bijan Davari ,  Scott Terrell Williams ,  Peter Anton Pechtl ,  Larry Keith McDonald ,  Alfred Ong'iro

IPC: G06G7/54 ,  G06F11/30

CPC classification number: G06F17/50 ,  G06F2217/78

Abstract: A computer-implemented method for modeling and/or improving operational performance of an energy system includes providing a graphical user interface configured to allow a user to manipulate equipment icons into an energy system model representation, using modular, piece-wise linear equipment models to simulate non-linear behavior of equipment represented by the manipulated equipment icons to solve an energy system model represented by the manipulation, and displaying a solution of the energy system model.

Abstract translation: 用于建模和/或改善能量系统的操作性能的计算机实现的方法包括提供图形用户界面，其被配置为允许用户使用模块化的分段线性设备模型来操纵设备图标到能量系统模型表示中，以模拟 由操纵设备图标表示的设备的非线性行为来解决由操纵所表示的能量系统模型，并显示能量系统模型的解决方案。

公开(公告)号：US07356383B2

公开(公告)日：2008-04-08

申请号：US11055312

申请日：2005-02-10

Applicant: Peter Anton Pechtl ,  Martin Posch ,  Bijan Davari ,  Marco Robert Dieleman

Inventor： Peter Anton Pechtl ,  Martin Posch ,  Bijan Davari ,  Marco Robert Dieleman

IPC: G05D19/00

CPC classification number: G05B19/41885 ,  G05B13/024 ,  Y02E20/14 ,  Y02E20/16 ,  Y02P80/154 ,  Y02P90/26

Abstract: Methods and systems for operating combined cycle electrical generating plants is provided. The method includes simulating the electrical power plant performance, simulating the steam utilizing process plant performance, parameterizing plant equipment and plant performance using the power plant and process plant simulation results, and solving parameterized simultaneous equations and constraints with an objective function to determine parameter settings that facilitate enhancing an efficiency of the combined cycle electrical generating/steam-utilizing process plant.

Abstract translation: 提供了操作联合循环发电厂的方法和系统。 该方法包括模拟电厂性能，模拟使用过程工厂性能的蒸汽，使用发电厂参数化设备设备和设备性能，以及过程工厂模拟结果，并用目标函数求解参数化的联立方程和约束，以确定参数设置 有助于提高联合循环发电/蒸汽利用过程工厂的效率。

公开(公告)号：US20070168174A1

公开(公告)日：2007-07-19

申请号：US11234438

申请日：2005-09-23

Applicant: Bijan Davari ,  Scott Williams ,  Peter Pechtl ,  Larry McDonald ,  Alfred Ong'iro

Inventor： Bijan Davari ,  Scott Williams ,  Peter Pechtl ,  Larry McDonald ,  Alfred Ong'iro

IPC: G06G7/48

CPC classification number: G06F17/50 ,  G06F2217/78

Abstract: A computer-implemented method for modeling and/or improving operational performance of an energy system includes providing a graphical user interface configured to allow a user to manipulate equipment icons into an energy system model representation, using modular, piece-wise linear equipment models to simulate non-linear behavior of equipment represented by the manipulated equipment icons to solve an energy system model represented by the manipulation, and displaying a solution of the energy system model.

Abstract translation: 用于建模和/或改善能量系统的操作性能的计算机实现的方法包括提供图形用户界面，其被配置为允许用户使用模块化的分段线性设备模型来操纵设备图标到能量系统模型表示中，以模拟 由操纵设备图标表示的设备的非线性行为来解决由操纵所表示的能量系统模型，并显示能量系统模型的解决方案。

公开(公告)号：US06333532B1

公开(公告)日：2001-12-25

申请号：US09356295

申请日：1999-07-16

Applicant: Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

Inventor： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

IPC: H01L27108

CPC classification number: H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep trench in bulk Si while forming merged logic regions on SOI.

Abstract translation: 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度处形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了在形成SOI上的合并逻辑区域的同时形成具有在体Si中的深沟槽的存储电容器形成DRAM的问题。

公开(公告)号：US5784311A

公开(公告)日：1998-07-21

申请号：US876177

申请日：1997-06-13

Applicant: Fariborz Assaderaghi ,  Bijan Davari ,  Louis L. Hsu ,  Jack A. Mandelman ,  Ghavam G. Shahidi

Inventor： Fariborz Assaderaghi ,  Bijan Davari ,  Louis L. Hsu ,  Jack A. Mandelman ,  Ghavam G. Shahidi

IPC: G11C8/16 ,  G11C11/404 ,  H01L27/108 ,  H01L27/12 ,  G11C11/24

CPC classification number: H01L27/1203 ,  G11C11/404 ,  G11C8/16 ,  H01L27/108

Abstract: A two-MOSFET device memory cell, based on conventional SOI complementary metal oxide technology, in which charge is stored on the body of a first MOSFET, with a second MOSFET connected to the body for controlling the charge in accordance with an information bit. Depending on the stored charge, the body of the first MOSFET is in depletion or non-depletion condition. A reference voltage connected to the gate of the first MOSFET causes a bipolar current flow in response to a pulsed voltage on the first MOSFET's source when the MOSFET is in a non-depletion condition, due to a temporary forward bias of the source to body junction. The bipolar current substantially adds to the field-effect current, thereby multiplying the effective charge read from the first MOSFET.

Abstract translation: 基于常规SOI互补金属氧化物技术的双MOSFET器件存储单元，其中电荷存储在第一MOSFET的主体上，其中第二MOSFET连接到主体以根据信息位来控制电荷。 取决于存储的电荷，第一个MOSFET的主体处于耗尽或非耗尽状态。 当MOSFET处于非耗尽状态时，连接到第一MOSFET的栅极的参考电压响应于第一MOSFET源极上的脉冲电压而导致双极电流流动，这是由于源至体结的临时向前偏置 。 双极性电流基本上增加了场效应电流，从而乘以从第一MOSFET读取的有效电荷。