公开(公告)号：US07453133B2

公开(公告)日：2008-11-18

申请号：US10880992

申请日：2004-06-30

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L27/095

CPC classification number: H01L23/3192 ,  H01L23/485 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract translation: 本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。 为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。 第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低， 半导体，优选低于1.1eV。 此外，可以在金属上沉积介电层。 电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。 还公开了制造该结构的过程。

公开(公告)号：US07342289B2

公开(公告)日：2008-03-11

申请号：US10637351

申请日：2003-08-08

Applicant: Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

Inventor： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

IPC: H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

Abstract translation: 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US07321155B2

公开(公告)日：2008-01-22

申请号：US10840911

申请日：2004-05-06

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L29/772

CPC classification number: H01L29/7845 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  Y10S257/90

Abstract: A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

Abstract translation: 应变沟道晶体管及其形成方法，所述应变沟道晶体管包括半导体衬底; 覆盖沟道区的栅极电介质; 覆盖栅极电介质的栅电极; 源极扩展（SDE）区域和源极和漏极（S / D）区域; 其特征在于，设置有选自由邻近所述栅电极配置的一对应力偏置间隔物和设置在包括所述S / D区域的所述栅极上方的应力介电层的应力电介质部分，以在沟道区域上施加应变。

公开(公告)号：US20060138557A1

公开(公告)日：2006-06-29

申请号：US11356865

申请日：2006-02-17

Applicant: Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

Abstract translation: 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。

公开(公告)号：US07045836B2

公开(公告)日：2006-05-16

申请号：US10657616

申请日：2003-09-08

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/00

CPC classification number: H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/66651

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

公开(公告)号：US07022561B2

公开(公告)日：2006-04-04

申请号：US10307619

申请日：2002-12-02

Applicant: Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Chien-Chao Huang ,  Chao-Hsing Wang ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828

Abstract: A method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices, wherein the first stress layer comprises a first tensile-stress layer or a compression-stress layer. An etch stop layer is formed over the first stress layer, and portions of the first stress layer and the etch stop layer are removed from over the NMOS device, leaving the first stress layer and the etch stop layer over the PMOS device. A second tensile-stress layer is formed over the NMOS device and over the first stress layer and the etch stop layer, and portions of the second tensile-stress layer and the etch stop layer are removed from over the PMOS device, leaving the second tensile-stress layer over the NMOS device.

Abstract translation: 一种方法，包括提供具有邻近PMOS器件的NMOS器件的衬底，并在所述NMOS和PMOS器件上形成第一应力层，其中所述第一应力层包括第一拉伸应力层或压缩应力层。 在第一应力层上形成蚀刻停止层，并且从NMOS器件上去除第一应力层和蚀刻停止层的部分，留下PMOS器件上的第一应力层和蚀刻停止层。 第二拉伸应力层形成在NMOS器件上并且在第一应力层和蚀刻停止层上方，并且第二拉伸应力层和蚀刻停止层的部分从PMOS器件上除去，留下第二拉伸 在NMOS器件上的应力层。

公开(公告)号：US06902965B2

公开(公告)日：2005-06-07

申请号：US10699574

申请日：2003-10-31

Applicant: Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/338 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L29/78 ,  H01L31/0328 ,  H01L31/072

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842

Abstract: A semiconductor device includes a substrate, a first epitaxial layer, a second epitaxial layer, a third epitaxial layer, a first trench, and a second trench. The first epitaxial layer is formed on the substrate. The first layer has lattice mismatch relative to the substrate. The second epitaxial layer is formed on the first layer, and the second layer has lattice mismatch relative to the first layer. The third epitaxial layer is formed on the second layer, and the third layer has lattice mismatch relative to the second layer. Hence, the third layer may be strained silicon. The first trench extends through the first layer. The second trench extends through the third layer and at least partially through the second layer. At least part of the second trench is aligned with at lease part of the first trench, and the second trench is at least partially filled with an insulating material.

Abstract translation: 半导体器件包括衬底，第一外延层，第二外延层，第三外延层，第一沟槽和第二沟槽。 第一外延层形成在基板上。 第一层相对于基底具有晶格失配。 第二外延层形成在第一层上，第二层相对于第一层具有晶格失配。 第三外延层形成在第二层上，第三层相对于第二层具有晶格失配。 因此，第三层可以是应变硅。 第一沟槽延伸穿过第一层。 第二沟槽延伸穿过第三层并且至少部分地穿过第二层。 第二沟槽的至少一部分与第一沟槽的至少部分对准，并且第二沟槽至少部分地填充有绝缘材料。

公开(公告)号：US06900502B2

公开(公告)日：2005-05-31

申请号：US10407761

申请日：2003-04-03

Applicant: Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

Inventor： Chung-Hu Ge ,  Chao-Hsuing Wang ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Chenming Hu

IPC: H01L21/00 ,  H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/02 ,  H01L29/72 ,  H01L29/772

CPC classification number: H01L21/823807 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7848

Abstract: A semiconductor device 10 includes a substrate 12 (e.g., a silicon substrate) with an insulating layer 14 (e.g., an oxide such as silicon dioxide) disposed thereon. A first semiconducting material layer 16 (e.g., SiGe) is disposed on the insulating layer 14 and a second semiconducting material layer 18 (e.g., Si) is disposed on the first semiconducting material layer 16. The first and second semiconducting material layers 16 and 18 preferably have different lattice constants such that the first semiconducting material layer 16 is compressive and the second semiconducting material layer is tensile 18.

Abstract translation: 半导体器件10包括其上设置有绝缘层14（例如氧化物如二氧化硅）的衬底12（例如，硅衬底）。 第一半导体材料层16（例如，SiGe）设置在绝缘层14上，并且第二半导体材料层18（例如，Si）设置在第一半导体材料层16上。 第一和第二半导体材料层16和18优选地具有不同的晶格常数，使得第一半导体材料层16是压缩的，并且第二半导体材料层是拉伸18。

公开(公告)号：US07495267B2

公开(公告)日：2009-02-24

申请号：US11409405

申请日：2006-04-21

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L31/0368

CPC classification number: H01L29/78 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L29/7846

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract translation: 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。

公开(公告)号：US20070161206A1

公开(公告)日：2007-07-12

申请号：US11586936

申请日：2006-10-26

Applicant: Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

Inventor： Chih-Hsin Ko ,  Yee-Chia Yeo ,  Wen-Chin Lee ,  Chung-Hu Ge

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/7846 ,  H01L29/7848

Abstract: A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

Abstract translation: 公开了用于形成用于应变通道晶体管的改进的隔离结构的方法和系统。 在一个示例中，形成包括填充有含氮衬里和间隙填料的沟槽的隔离结构。 含氮衬垫使隔离结构能够减小对通道区域的压应变贡献。