公开(公告)号：US20100277983A1

公开(公告)日：2010-11-04

申请号：US12835423

申请日：2010-07-13

申请人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

发明人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/107 ,  G11C16/3404 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 存储器单元的子集在擦除之前被预处理。 预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。 作为示例，沿着单个字线的存储器单元可以被预处理。 在预处理之后，使用试写擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US20100261317A1

公开(公告)日：2010-10-14

申请号：US12822568

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： H01L21/82 ,  H01L21/336

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

公开(公告)号：US20100009503A1

公开(公告)日：2010-01-14

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US07623389B2

公开(公告)日：2009-11-24

申请号：US11614884

申请日：2006-12-21

申请人： Dana Lee ,  Jeffrey Lutze

发明人： Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： System for programming a selected non-volatile memory cell in a memory array having a gate node coupled to a wordline WL(n) and a drain node connected to a selected bitline by injecting hot carriers from a drain region of an injecting memory cell having a gate node coupled to a next neighbor wordline WL(n−1) into a floating gate of the selected non-volatile memory cell on the wordline WL(n).

摘要翻译： 用于通过从注入存储器单元的漏极区域注入热载流子来对存储器阵列中的所选择的非易失性存储单元进行编程的系统，所述存储器阵列具有耦合到字线WL（n）的栅极节点和连接到所选位线的漏极节点 门节点与下一个相邻字线WL（n-1）耦合到字线WL（n）上的所选择的非易失性存储器单元的浮动栅极。

公开(公告)号：US20090016118A1

公开(公告)日：2009-01-15

申请号：US11777138

申请日：2007-07-12

申请人： Yuniarto Widjaja ,  Dana Lee

发明人： Yuniarto Widjaja ,  Dana Lee

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/10802 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/42324 ,  H01L29/7841 ,  H01L29/7881

摘要： A non-volatile capacitor-less 1T DRAM has a semiconductor substrate of a first conducting type with a surface. A first region of a second conductivity type is in the substrate on the surface. A second region of the second conductivity type is in the substrate on the surface, spaced apart from the first region. A body region of the first conductivity type is in the substrate between the first region and the second region. The body region is bound by the surface, one or more insulating regions and the first and second regions. The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region. A control gate is capacitively coupled to the floating gate.

摘要翻译： 非易失性电容器1T DRAM具有表面的第一导电类型的半导体衬底。 第二导电类型的第一区域在表面上的衬底中。 第二导电类型的第二区域在表面上的衬底中，与第一区域间隔开。 第一导电类型的体区在第一区域和第二区域之间的衬底中。 身体区域由表面，一个或多个绝缘区域和第一和第二区域结合。 DRAM还具有与表面绝缘的浮动栅极，并且位于第一区域和第二区域之间。 控制栅极电容耦合到浮动栅极。

公开(公告)号：US20080159004A1

公开(公告)日：2008-07-03

申请号：US11618600

申请日：2006-12-29

申请人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

发明人： Gerrit Jan Hemink ,  Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at different voltages for particular non-volatile storage elements.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于特定的非易失性存储元件，以不同的电压提供一个或多个预充电使能信号。

公开(公告)号：US20080159002A1

公开(公告)日：2008-07-03

申请号：US11618580

申请日：2006-12-29

申请人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

发明人： Yingda Dong ,  Jeffrey W. Lutze ,  Dana Lee ,  Gerrit Jan Hemink

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C7/1048 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Unselected groups of non-volatile storage elements are boosted during programming to reduce or eliminate program disturb for targeted, but unselected memory cells connected to a selected word line. Prior to applying a program voltage to the selected word line and boosting the unselected groups, the unselected groups are pre-charged to further reduce or eliminate program disturb by providing a larger boosted potential for the unselected groups. During pre-charging, one or more pre-charge enable signals are provided at higher voltages for certain memory cells that may have undergone partial programming.

摘要翻译： 在编程期间，未选择的非易失性存储元件组被提升以减少或消除连接到所选字线的目标但未选择的存储器单元的程序干扰。 在将程序电压施加到所选择的字线并升高未选择的组之前，未选择的组被预先充电，以通过为未选择的组提供更大的增强电位来进一步减少或消除程序干扰。 在预充电期间，对于可能已经经过部分编程的某些存储器单元，在较高电压下提供一个或多个预充电使能信号。

公开(公告)号：US20080084761A1

公开(公告)日：2008-04-10

申请号：US11535452

申请日：2006-09-26

申请人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

发明人： Dana Lee ,  Yingda Dong ,  Changyuan Chen ,  Jeffrey Lutze

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A hybrid method of programming a non-volatile memory cell to a final programmed state is described. The method described is a more robust protocol suitable for reliably programming selected memory cells while eliminating programming disturbs. The hybrid method comprises programming the non-volatile memory cell to a first state according to a first coarse programming mechanism, and programming the non-volatile memory cell according to a second different more precise programming mechanism thereby completing the programming of the non-volatile memory cell to the final programmed state. Additionally, the described method is particularly advantageous for programming multilevel chips.

摘要翻译： 描述了将非易失性存储器单元编程到最终编程状态的混合方法。 所描述的方法是一种更鲁棒的协议，适用于可靠地编程所选择的存储器单元，同时消除编程干扰。 混合方法包括根据第一粗略编程机制将非易失性存储器单元编程为第一状态，以及根据第二种不同的更精确的编程机制对非易失性存储器单元进行编程，由此完成非易失性存储器的编程 单元格到最终编程状态。 另外，所描述的方法对于编程多级芯片是特别有利的。

公开(公告)号：US07247907B2

公开(公告)日：2007-07-24

申请号：US11134557

申请日：2005-05-20

申请人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

发明人： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

公开(公告)号：US07242051B2

公开(公告)日：2007-07-10

申请号：US11134540

申请日：2005-05-20

申请人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

发明人： Yuniarto Widjaja ,  John W. Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC分类号： H01L29/788

CPC分类号： G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.