公开(公告)号：US11651802B1

公开(公告)日：2023-05-16

申请号：US17455292

申请日：2021-11-17

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/146 ,  G11C7/1045 ,  G11C7/1096

Abstract: The present disclosure is drawn to, among other things, a method for accessing memory using dual standby modes, the method including receiving a first standby mode indication selecting a first standby mode from a first standby mode or a second standby mode, configuring a read bias system to provide a read bias voltage and a write bias system to provide approximately no voltage, or any voltage outside the necessary range for write operation, based on the first standby mode, receiving a second standby mode indication selecting the second standby mode, and configuring the read bias system to provide at least the read bias voltage and the write bias system to provide a write bias voltage based on the second standby mode, the read bias voltage being lower than the write bias voltage.

公开(公告)号：US20220343030A1

公开(公告)日：2022-10-27

申请号：US17660253

申请日：2022-04-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Sanjeev AGGARWAL

IPC: G06F21/72 ,  G06F21/86 ,  H01F10/32 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a storage device. The storage device may include a magnetic tunnel junction (MTJ)-based storage array and a communication interface. The MTJ-based storage array may be configured to be damaged by a shorting voltage based on detection of a tamper event.

公开(公告)号：US11436087B2

公开(公告)日：2022-09-06

申请号：US15993046

申请日：2018-05-30

Applicant: Everspin Technologies, Inc.

Inventor： Pankaj Bishnoi ,  Trevor Sydney Smith ,  James MacDonald

IPC: G06F11/00 ,  G06F11/14 ,  G06F1/30 ,  G06F3/06 ,  G06F12/02

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes receiving data to be stored in a storage memory, wherein the storage memory is coupled to the memory device, wherein the memory device includes a first memory type and a second memory type different from the first memory type; storing a first copy of the received data in the first memory type; storing a second copy of the received data in the second memory type; receiving indication of a power loss to the memory device; in response to receiving indication of the power loss, copying the second copy from the second memory type to the storage memory; detecting for power restoration to the memory device after the power loss; and in response to detecting power restoration to the memory device, restoring data to the first memory type by copying data from the second memory type to the first memory type.

公开(公告)号：US20220260651A1

公开(公告)日：2022-08-18

申请号：US17735185

申请日：2022-05-03

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Bradley Neal ENGEL ,  Phillip G. MATHER

IPC: G01R33/00 ,  G01R33/09 ,  G01R33/06

Abstract: A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor includes a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each TMR element. The current lines are serially or sequentially connected to a current source to receive the bipolar current pulse. The field sensor has an output including a high output and a low output in response to the bipolar pulse. This asymmetric response allows a chopping technique for 1/f noise reduction in the field sensor.

公开(公告)号：US11176974B2

公开(公告)日：2021-11-16

申请号：US16518146

申请日：2019-07-22

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas S. Andre

IPC: G11C7/12 ,  G11C7/06 ,  G11C5/06

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

公开(公告)号：US11139429B2

公开(公告)日：2021-10-05

申请号：US16794449

申请日：2020-02-19

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Kerry Nagel ,  Jason Janesky

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.

公开(公告)号：US11088318B2

公开(公告)日：2021-08-10

申请号：US16376644

申请日：2019-04-05

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: Spin-orbit-torque (SOT) lines are provided near free regions in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT lines injects spin current into the free regions such that spin torque is applied to the free regions. The spin torque generated from a SOT switching line can be used to switching the free region or to act as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction, in order to improve the reliability, endurance, or both of the magnetoresistive device. Further, one or more additional layers or regions may improve the SOT switching efficiency and the thermal stability of magnetoresistive devices including SOT lines.

公开(公告)号：US20210234090A1

公开(公告)日：2021-07-29

申请号：US16750264

申请日：2020-01-23

Applicant: Everspin Technologies, Inc.

Inventor： SHIMON

IPC: H01L43/06 ,  H01L43/04 ,  H01L43/10 ,  H01L43/14 ,  G11C11/16

Abstract: The magnetoresistive stack or structure of a magnetoresistive device includes one or more electrodes or electrically conductive lines, a magnetically fixed region, a magnetically free region disposed between the electrodes or electrically conductive lines, and a dielectric layer disposed between the free and fixed regions. The magnetoresistive device may further include a spin-Hall (SH) material proximate to at least a portion of the free region, and one or more insertion layers comprising antiferromagnetic material.

公开(公告)号：US20210199729A1

公开(公告)日：2021-07-01

申请号：US17146516

申请日：2021-01-12

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Bradley Neal ENGEL ,  Phillip G. MATHER

IPC: G01R33/00 ,  G01R33/09 ,  G01R33/06

Abstract: A chopping technique, and associated structure, is implemented to cancel the magnetic 1/f noise contribution in a Tunneling Magnetoresistance (TMR) field sensor. The TMR field sensor includes a first bridge circuit including multiple TMR elements to sense a magnetic field and a second circuit to apply a bipolar current pulse adjacent to each TMR element. The current lines are serially or sequentially connected to a current source to receive the bipolar current pulse. The field sensor has an output including a high output and a low output in response to the bipolar pulse. This asymmetric response allows a chopping technique for 1/f noise reduction in the field sensor.

公开(公告)号：US11043630B2

公开(公告)日：2021-06-22

申请号：US16695396

申请日：2019-11-26

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev Aggarwal ,  Sarin A. Deshpande

IPC: H01L43/04 ,  H01L21/3065 ,  H01L43/14

Abstract: A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region. An insulator region may extend around a portion of the sidewall such that the insulator region contacts a first portion of the sidewall and the spin Hall channel region contacts a second portion of the sidewall.