公开(公告)号：US20040238970A1

公开(公告)日：2004-12-02

申请号：US10868066

申请日：2004-06-16

申请人： Endicott Interconnect Technologies, Inc.

发明人： David J. Alcoe

IPC分类号： H01L023/48

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  H01L2224/0401

摘要： A circuitized substrate which utilizes an underlying conductive layer coupled to a pad on the substrate to assure a reinforced pad which will not be damaged or removed from the substrate when subjected to a significant load. Two or more pads can be similarly provided and coupled to the conductive layer, e.g., the layer being a common (ground) layer. An information handling system (e.g., a personal computer) utilizing the substrate is also provided.

摘要翻译： 电路化基板，其利用与基板上的焊盘耦合的下层导电层，以确保在经受显着载荷时不会损坏或从基板移除的加强垫。 可以类似地提供两个或更多个焊盘并耦合到导电层，例如该层是公共（接地）层。 还提供了利用该基板的信息处理系统（例如个人计算机）。

公开(公告)号：US20040150969A1

公开(公告)日：2004-08-05

申请号：US10354000

申请日：2003-01-30

申请人： Endicott Interconnect Technologies Inc.

发明人： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC分类号： H05K001/11

CPC分类号： H05K3/4688 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

公开(公告)号：US20040150114A1

公开(公告)日：2004-08-05

申请号：US10394107

申请日：2003-03-24

申请人： Endicott Interconnect Technologies, Inc.

发明人： Lawrence R. Fraley ,  Voya R. Markovich

IPC分类号： H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC分类号： H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

摘要： A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

摘要翻译： 一种多芯片电子封装，其利用位于载体的上表面上的有机层压芯片载体和多个半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片连接到其底表面上的底层导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。

公开(公告)号：US20040150095A1

公开(公告)日：2004-08-05

申请号：US10661616

申请日：2003-09-15

申请人： Endicott Interconnect Technologies, Inc.

发明人： Lawrence R. Fraley ,  Voya Markovich

IPC分类号： H01L023/538

CPC分类号： H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

摘要： A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

摘要翻译： 一种多芯片电子封装，其利用位于载体的上表面上的堆叠取向的有机层压芯片载体和一对半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片中的一个或两个耦合到其底表面上的下面的导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。 第一芯片（例如ASIC芯片）被焊接到载体上，而第二芯片（例如存储器芯片）被固定到第一芯片的上表面并且使用多个引线键合连接到载体。