公开(公告)号：US20070040207A1

公开(公告)日：2007-02-22

申请号：US11586291

申请日：2006-10-25

Applicant: Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

Inventor： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

IPC: H01L29/00

CPC classification number: H01L21/02186 ,  C23C16/405 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

Abstract translation: 形成电子器件的方法包括提供第一电极，在第一电极上提供电介质氧化物层，并在电介质氧化物层上提供第二电极，使得电介质氧化物层位于第一和第二电极之间。 更具体地，与第一电极相邻的电介质氧化物层的第一部分可以具有第一密度的钛，并且与第一电极相对的电介质氧化物层的第二部分可具有不同于第一密度的钛的第二密度。 还讨论了相关结构。

公开(公告)号：US20160104705A1

公开(公告)日：2016-04-14

申请号：US14754400

申请日：2015-06-29

Applicant: Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

Inventor： Eun-ae Chung ,  Jung-dal Choi ,  Toshiro Nakanishi ,  Yu-bin Kim ,  Gab-jin Nam ,  Dong-kyu Lee ,  Guangfan Jiao

IPC: H01L27/088 ,  H01L27/12

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/1211

Abstract: A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

Abstract translation: 半导体器件包括具有其上包括逻辑器件的逻辑器件区域的衬底，以及在其上邻近逻辑器件区域的包括I / O器件的输入/输出（I / O）器件区域。 逻辑器件区域上的第一鳍状场效应晶体管（FinFET）包括从衬底突出的第一半导体鳍片，以及在其上具有第一栅极电介质层和第一栅极电极的三栅极结构。 I / O器件区域上的第二FinFET包括从衬底突出的第二半导体鳍片，以及在其上具有第二栅极介电层和第二栅电极的双栅极结构。 第一和第二栅极电介质层具有不同的厚度。 还讨论了相关设备和制造方法。

公开(公告)号：US20140291755A1

公开(公告)日：2014-10-02

申请号：US14167053

申请日：2014-01-29

Applicant: Sung-Kweon BAEK ,  Gab-Jin NAM ,  Jin-Soak KIM ,  Ji-Young MIN ,  Eun-Ae CHUNG

Inventor： Sung-Kweon BAEK ,  Gab-Jin NAM ,  Jin-Soak KIM ,  Ji-Young MIN ,  Eun-Ae CHUNG

IPC: H01L29/423 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L29/7827

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Abstract translation: 半导体器件包括设置在半导体衬底的有源区中的第一源极/漏极区域和第二源极/漏极区域以及与有源区域交叉并设置在第一和第二源极/漏极区域之间的栅极结构，栅极结构 包括在第一部分具有第一部分和第二部分的栅电极，栅电极处于比有源区的上表面更低的电平，栅电极上的绝缘封盖图案，栅电极之间的栅极电介质 和有源区，以及有源区和栅电极的第二部分之间的空白空间。

公开(公告)号：US08785267B2

公开(公告)日：2014-07-22

申请号：US13613868

申请日：2012-09-13

Applicant: Sung-kweon Baek ,  Jin-soak Kim ,  Gab-jin Nam ,  Ji-young Min ,  Eun-ae Chang

Inventor： Sung-kweon Baek ,  Jin-soak Kim ,  Gab-jin Nam ,  Ji-young Min ,  Eun-ae Chang

IPC: H01L21/338 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/28185 ,  H01L21/3115 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulation layer pattern on a substrate, forming a sacrificial layer including impurities on the gate insulation layer pattern, annealing the sacrificial layer so that the impurities in the sacrificial layer diffuse into the gate insulation layer pattern, removing the sacrificial layer, and forming a gate electrode on the gate insulation layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅极绝缘层图案，在栅极绝缘层图案上形成包括杂质的牺牲层，使牺牲层退火，使牺牲层中的杂质扩散到栅极绝缘层图案中 去除牺牲层，以及在栅极绝缘层图案上形成栅电极。

公开(公告)号：US07910421B2

公开(公告)日：2011-03-22

申请号：US12130646

申请日：2008-05-30

Applicant: Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

Inventor： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

IPC: H01L29/66

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

Abstract: Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

Abstract translation: 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

公开(公告)号：US07585756B2

公开(公告)日：2009-09-08

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin Nam ,  Myoung-Bum Lee

Inventor： Gab-Jin Nam ,  Myoung-Bum Lee

IPC: H01L21/3205

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US07482677B2

公开(公告)日：2009-01-27

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L21/4763

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。

公开(公告)号：US20080067581A1

公开(公告)日：2008-03-20

申请号：US11896834

申请日：2007-09-06

Applicant: Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

Inventor： Sug-Hun Hong ,  Myoung-Bum Lee ,  Gab-Jin Nam

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L29/66833 ,  H01L29/7923

Abstract: A non-volatile memory device includes a tunnel insulating layer pattern on a channel region of a substrate, a charge trapping layer pattern on the tunnel insulating layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode including a conductive layer pattern on the blocking layer pattern and a barrier layer pattern on the conductive layer pattern. The conductive layer pattern includes a metal

Abstract translation: 非易失性存储器件包括在衬底的通道区域上的隧道绝缘层图案，隧道绝缘层图案上的电荷俘获层图案，电荷俘获层图案上的阻挡层图案，以及包括导电 阻挡层图案上的层图案和导电层图案上的阻挡层图案。 导电层图案包括金属

公开(公告)号：US20080042173A1

公开(公告)日：2008-02-21

申请号：US11839387

申请日：2007-08-15

Applicant: Gab-Jin NAM ,  Myoung-Bum LEE

Inventor： Gab-Jin NAM ,  Myoung-Bum LEE

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/78

Abstract: A MOS transistor includes a substrate, source/drain regions formed at portions of the substrate, and a channel region formed between the source/drain regions. The MOS transistor further includes a gate structure having a gate insulation layer pattern and a gate electrode formed on the channel region. The gate electrode includes a first gate conductive layer pattern and a second gate conductive layer pattern. The first gate conductive layer pattern has a nitrogen concentration gradient gradually increasing from a lower portion of the first gate conductive layer pattern to an upper portion of the first gate conductive layer pattern. The second gate conductive layer pattern includes a material having a resistance substantially lower than a resistance of the first gate conductive layer pattern.

Abstract translation: MOS晶体管包括衬底，形成在衬底的部分处的源极/漏极区域和形成在源极/漏极区域之间的沟道区域。 MOS晶体管还包括具有栅极绝缘层图案的栅极结构和形成在沟道区上的栅电极。 栅电极包括第一栅极导电层图案和第二栅极导电层图案。 第一栅极导电层图案具有从第一栅极导电层图案的下部逐渐增加到第一栅极导电层图案的上部的氮浓度梯度。 第二栅极导电层图案包括具有基本上低于第一栅极导电层图案的电阻的电阻的材料。

公开(公告)号：US20060244147A1

公开(公告)日：2006-11-02

申请号：US11339086

申请日：2006-01-25

Applicant: Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

Inventor： Jong-Cheol Lee ,  Sung-Tae Kim ,  Young-Sun Kim ,  Cha-Young Yoo ,  Gab-Jin Nam ,  Young-Geun Park ,  Jae-Hyoung Choi ,  Jae-Hyun Yeo ,  Ha-Jin Lim ,  Yun-Seok Kim

IPC: H01L23/48

CPC classification number: H01L21/022 ,  H01L21/02142 ,  H01L21/02156 ,  H01L21/02175 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/11502 ,  H01L27/11521

Abstract: In a method of manufacturing a dielectric structure, after a tunnel oxide layer pattern is formed on a substrate, a floating gate is formed on the tunnel oxide layer. After a first dielectric layer pattern including a metal silicon oxide and a second dielectric layer pattern including a metal silicon oxynitride are formed, a control gate is formed on the dielectric structure. Since the dielectric structure includes at least one metal silicon oxide layer and at least one metal silicon oxynitride layer, the dielectric structure may have a high dielectric constant and a good thermal resistance. A non-volatile semiconductor memory device including the dielectric structure may have good electrical characteristics such as a large capacitance and a low leakage current.

Abstract translation: 在制造电介质结构的方法中，在衬底上形成隧道氧化物层图案之后，在隧道氧化物层上形成浮栅。 在形成包括金属氧化硅和包括金属氮氧化硅的第二电介质层图案的第一电介质层图案之后，在电介质结构上形成控制栅极。 由于介电结构包括至少一个金属氧化硅层和至少一个金属氮氧化硅层，所以介电结构可以具有高介电常数和良好的耐热性。 包括电介质结构的非易失性半导体存储器件可能具有良好的电特性，例如大电容和低漏电流。