公开(公告)号：US06387716B1

公开(公告)日：2002-05-14

申请号：US09522054

申请日：2000-03-09

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L2166

CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly-distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon-containing material.

Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在无规分布的介电层特征上而不是在其它基底区域上。 随后检查衬底以进行选择性沉积的含硅材料。

公开(公告)号：US06368919B2

公开(公告)日：2002-04-09

申请号：US09233313

申请日：1999-01-19

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L21336

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US5976990A

公开(公告)日：1999-11-02

申请号：US004931

申请日：1998-01-09

Applicant: Garry A. Mercaldi ,  Michael L. Nuttall ,  Randhir P. S. Thankur

Inventor： Garry A. Mercaldi ,  Michael L. Nuttall ,  Randhir P. S. Thankur

IPC: C23C16/34 ,  C23C16/44 ,  H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/44 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/90

Abstract: An exemplary implementation of the present invention discloses a semiconductor fabrication method for forming a film in a reactor. Process conditions (temperature and pressure) are initially stabilized prior to a film deposition cycle. Once process conditions are stable, chemical elements of are nucleated onto a substrate surface to form a nucleation surface of the film. The bulk portion of the film is then deposited onto the nucleation surface. Finally, after the bulk of the film is deposited the surface of the film is conditioned. To tailor a film the process conditions are varied during the film deposition cycle wherein at least one of the pressures and temperatures is varied by at least 10%. In a specific implementation, a capacitor dielectric of silicon nitride is tailored by varying the pressure for the bulk film deposition and by varying both the temperature and pressure for the film surface formation phase.

Abstract translation: 本发明的示例性实施方式公开了一种用于在反应器中形成膜的半导体制造方法。 在膜沉积循环之前，工艺条件（温度和压力）最初是稳定的。 一旦工艺条件稳定，将化学元素成核到基底表面上以形成膜的成核表面。 然后将膜的主体部分沉积到成核表面上。 最后，在沉积膜的大部分之后，调节膜的表面。 为了定制薄膜，工艺条件在成膜周期期间是变化的，其中至少一个压力和温度变化至少10％。 在具体实施方式中，氮化硅的电容器电介质通过改变体膜沉积的压力并通过改变膜表面形成阶段的温度和压力来调整。

公开(公告)号：US07642157B2

公开(公告)日：2010-01-05

申请号：US11510949

申请日：2006-08-28

Applicant: Donald L Yates ,  Garry A Mercaldi

Inventor： Donald L Yates ,  Garry A Mercaldi

IPC: H01L21/8242

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

Abstract translation: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中，通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料，然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构，导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上，导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中，通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中，并且聚集到构造层的表面位错上，形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。

公开(公告)号：US06833084B2

公开(公告)日：2004-12-21

申请号：US09285773

申请日：1999-04-05

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。

公开(公告)号：US06794704B2

公开(公告)日：2004-09-21

申请号：US10050390

申请日：2002-01-16

Applicant: Donald L. Yates ,  Garry A. Mercaldi ,  James J. Hofmann

Inventor： Donald L. Yates ,  Garry A. Mercaldi ,  James J. Hofmann

IPC: H01L27108

CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

Abstract: Lower electrodes of capacitors composed of a texturizing underlayer and a conductive material overlayer are provided. The lower electrodes have an upper roughened surface. In one embodiment, the texturizing layer is composed of porous or relief nanostructures comprising a polymeric material, for example, silicon oxycarbide. In another embodiment, the texturizing underlayer is in the form of surface dislocations composed of annealed first and second conductive metal layers, and the conductive metal overlayer is agglomerated onto the surface dislocations as nanostructures in the form of island clusters.

Abstract translation: 提供了由纹理化底层和导电材料覆盖层组成的电容器的下部电极。 下部电极具有上部粗糙表面。 在一个实施方案中，组织化层由包含聚合物材料的多孔或释放纳米结构组成，例如碳氧化硅。 在另一个实施方案中，所述织构化底层是由退火的第一和第二导电金属层组成的表面位错的形式，并且所述导电金属覆层作为岛簇形式的纳米结构聚集到所述表面位错上。

公开(公告)号：US06682970B1

公开(公告)日：2004-01-27

申请号：US09692897

申请日：2000-10-19

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: H01L218242

CPC classification number: H01L27/11502 ,  G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L27/11507 ,  H01L28/60 ,  H01L28/84

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier material.

Abstract translation: 半导体结构包括具有第一和第二相对侧的电介质层。 导电层与电介质层的第一侧相邻并且耦合到第一端子，并且导电阻挡层与电介质层的第二侧相邻并耦合到第二端子。 导电阻挡层可以由氮化钨，氮化钨，氮化钛或其它阻挡材料形成。

公开(公告)号：US06521945B2

公开(公告)日：2003-02-18

申请号：US10060532

申请日：2002-01-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L29792

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511 ,  Y10S438/954

Abstract: A dielectric insulating composite for insulating a floating gate from a control gate in a non-volatile memory is described. A material, such as an undoped polysilicon, amorphous silicon, or amorphous polysilicon or a silicon rich nitride, is inserted in the gate structure. The oxide film that results from the oxidation of these films is relatively free from impurities. As a result, charge leakage between the floating gate and control gate is reduced.

公开(公告)号：US06251693B1

公开(公告)日：2001-06-26

申请号：US09126983

申请日：1998-07-30

Applicant: Michael Nuttall ,  Garry A. Mercaldi

Inventor： Michael Nuttall ,  Garry A. Mercaldi

IPC: H01L2166

CPC classification number: H01L22/24 ,  Y10S438/928 ,  Y10S438/974

Abstract: Semiconductor processing methods and defect detection methods are described. In one embodiment, a semiconductor wafer in process is provided and a material is formed or deposited over the wafer. The material is discernably deposited over defective wafer surface areas and not appreciably deposited over non-defective wafer surface areas. Subsequently, the wafer surface areas are inspected to identify defective areas. In another embodiment, a substrate is provided having an exposed region containing surface defects. A defect-highlighting material is substantially selectively deposited over surface defects and not appreciably over other exposed regions. The substrate is subsequently inspected for the deposited defect-highlighting material. In yet another embodiment, a dielectric layer is formed over a substrate outer surface and the substrate is processed in a manner which can give rise to a plurality of randomly-distributed dielectric layer features. A silicon-containing material is substantially selectively deposited and received over the randomly-distributed dielectric layer features and not over other substrate areas. The substrate is subsequently inspected for the selectively-deposited silicon-containing material.

Abstract translation: 描述半导体处理方法和缺陷检测方法。 在一个实施例中，提供了工艺中的半导体晶片，并且在晶片上形成或沉积材料。 该材料可辨别地沉积在缺陷晶片表面区域上，并且不会明显地沉积在无缺陷晶片表面区域上。 随后，检查晶片表面区域以识别缺陷区域。 在另一个实施例中，提供具有包含表面缺陷的暴露区域的衬底。 缺陷突出材料基本上选择性地沉积在表面缺陷上，而不是明显地超过其它暴露区域。 随后检查衬底以便沉积的缺陷突出材料。 在另一个实施例中，在衬底外表面上形成电介质层，并且以可以产生多个随机分布的电介质层特征的方式处理衬底。 基本上选择性地沉积含硅材料并将其接收在无规分布的介电层特征上而不是在其它基底区域上。 随后检查衬底以进行选择性沉积的含硅材料。

公开(公告)号：US6150706A

公开(公告)日：2000-11-21

申请号：US32182

申请日：1998-02-27

Applicant: Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

Inventor： Randhir P. S. Thakur ,  Garry A. Mercaldi ,  Michael Nuttall

IPC: G11C11/404 ,  G11C17/16 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L29/00

CPC classification number: G11C11/404 ,  G11C17/16 ,  H01L21/28568 ,  H01L21/76888 ,  H01L27/1085 ,  H01L28/60

Abstract: A semiconductor structure includes a dielectric layer having first and second opposing sides. A conductive layer is adjacent to the first side of the dielectric layer and is coupled to a first terminal, and a conductive barrier layer is adjacent to the second side of the dielectric layer and is coupled to a second terminal. The conductive barrier layer may be formed from tungsten nitride, tungsten silicon nitride, titanium silicon nitride or other barrier materials.