公开(公告)号：US12191880B2

公开(公告)日：2025-01-07

申请号：US18083823

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Ewout Martens ,  Jan Craninckx

IPC: H03M1/16 ,  H03M1/12 ,  H03M1/56

Abstract: A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.

公开(公告)号：US12188895B2

公开(公告)日：2025-01-07

申请号：US17692717

申请日：2022-03-11

Applicant: IMEC VZW

Inventor： David Barge ,  Bert Du Bois ,  Simone Severi ,  Ashesh Ray Chaudhuri

IPC: H01L21/00 ,  G01N27/414

Abstract: A method for forming a nanopore transistor and a nanopore transistor is provided. The method includes: (a) forming an aperture in a filler material by: (i) providing a fin comprising a semiconductor layer and a top layer; (ii) patterning the top layer to form a pillar; (iii) embedding the pillar in a filler material; (iv) removing the pillar, leaving an aperture; (v) lining the aperture with a spacer material; (b) forming a nanopore by etching through the aperture; (b) lining the nanopore with a dielectric, (c) forming a source and a drain by either: between steps a.ii and a.iii, doping the bottom semiconductor layer by using the pillar as a mask, or after step c, filling the aperture with a sealing material, thereby forming a post; removing the filler material; doping the bottom semiconductor layer by using the post as a mask; and removing the sealing material.

公开(公告)号：US20240404273A1

公开(公告)日：2024-12-05

申请号：US18796196

申请日：2024-08-06

Applicant: Imec vzw ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Ruoyu Feng ,  Andre Bourdoux ,  Hichem Sahli ,  Sofie Pollin

IPC: G06V20/00 ,  G01S13/72 ,  G01S13/89 ,  G06T7/277

Abstract: A method is provided for indoor multipath ghosts recognition for a multiple-input-multiple-output radar with collocated antennas. The method includes the step of generating a two-dimensional Range-Doppler map for N number of consecutive radar data frames. The method further includes the step of applying a temporal clustering algorithm to the N number of consecutive radar data frames. Moreover, the method includes the step of applying a linear pattern extraction algorithm on the two-dimensional Range-Doppler map. In this context, the two-dimensional Range-Doppler map comprises detections from at least one target, at least one first-order ghost, and at least one second-order ghost with respect to one wall reflector.

公开(公告)号：US12154979B2

公开(公告)日：2024-11-26

申请号：US17496186

申请日：2021-10-07

Applicant: IMEC VZW

Inventor： Aryan Afzalian

IPC: H01L29/772 ,  H03K17/687

Abstract: A field-effect transistor and a method for controlling such is provided herein. The field-effect transistor includes a source terminal and a drain terminal arranged on a first side of a semiconductor layer and a single gate arranged on a second side of the semiconductor layer opposite the first side. The gate and the source terminal are arranged to overlap with a first common region of the semiconductor layer and the gate and the drain terminal are arranged to overlap with a second common region of the semiconductor layer.

公开(公告)号：US12154830B2

公开(公告)日：2024-11-26

申请号：US17580020

申请日：2022-01-20

Applicant: IMEC vzw

Inventor： Gaspard Hiblot ,  Anshul Gupta ,  Geert Van Der Plas

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of producing a gate cut in a semiconductor component is provided. In one aspect, an array of nano-sized semiconductor fins is processed on a semiconductor substrate. Rails may be buried in the substrate and in a layer of dielectric material that isolates neighboring fins from each other. The rails may extend in the direction of the fins and each rail may be situated between two adjacent fins. The rails may be buried power rails for enabling the formation of a power delivery network at the back of an integrated circuit chip. At the front side of the substrate, one or more gate structures are produced. The gate structures extend transversally, or perpendicularly, with respect to the fins and the rails. A gate cut is produced by forming an opening from the back side of the substrate, and removing a portion of the gate structure at the bottom of the opening, thereby creating a gate cut that is aligned to the sidewalls of the rail. In another aspect, a semiconductor component, such as an integrated circuit, includes a gate cut that is aligned to the sidewalls of a buried contact rail.

公开(公告)号：US20240383187A1

公开(公告)日：2024-11-21

申请号：US18693050

申请日：2022-09-20

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Behnam MADADNIA ,  Jan VANFLETEREN ,  Frederick BOSSUYT

IPC: B29C51/14 ,  B29K75/00 ,  B29K105/20 ,  B29L31/34 ,  B32B3/30 ,  B32B7/12 ,  B32B27/08 ,  B32B27/40 ,  H01L33/62

Abstract: The disclosure relates to a method for manufacturing a shape-retaining non-flat device (100), comprising: providing (S10) a flat device laminate (200) comprising: a first layer of thermoformable material (210); a carrier layer (230); conductive traces (240) arranged at least on a second portion (232) of the carrier layer (230); a circuit element (250) arranged on the second portion (232) and electrically connected to the conductive traces (240); deforming (S20) the device region (260) of the flat device laminate (200) into the shape-retaining non-flat device (100) by thermoforming (S22) the flat device laminate (200), wherein the carrier layer (230) is non-stretchable such that the respective shortest distance (d), along the second portion (232) of the carrier layer (230), between the circuit element (250) and a first portion (231), prior to and after the step of deforming (S20) the flat device laminate (200), are equal.

公开(公告)号：US12146873B2

公开(公告)日：2024-11-19

申请号：US17849905

申请日：2022-06-27

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Pol Van Dorpe

IPC: G01N15/06 ,  G01N15/01 ,  G01N33/487

Abstract: A method of operating a pore field-effect transistor (FET) sensor for detecting particles, wherein the pore FET sensor comprises a FET wherein a gate is controlled by a pore filled by a fluid, comprises: controlling a first voltage (Vcis) to set the FET in a subthreshold region; controlling a second voltage (Vtrans) to set a voltage difference between the first and second voltages (Vtrans) such that an effective difference in gate voltage experienced between a minimum and a maximum effective gate voltage during movement of a particle in the fluid is at least kT/q; and detecting a drain-source current in the FET, wherein the particle passing through the pore modulates the drain-source current for detecting presence of the particle.

公开(公告)号：US12127957B2

公开(公告)日：2024-10-29

申请号：US17298674

申请日：2019-11-28

Applicant: Universiteit Gent ,  IMEC VZW

Inventor： Rik Verplancke ,  Jan Vanfleteren

IPC: A61F2/86 ,  A61N5/06

CPC classification number: A61F2/86 ,  A61N5/0601 ,  A61N5/0622 ,  A61F2210/0014 ,  A61F2210/0057 ,  A61F2220/005 ,  A61F2250/006 ,  A61N2005/0602 ,  A61N2005/0632 ,  A61N2005/0652

Abstract: The present invention relates to a method for integrating an electronic circuit in or on a medical stent. The method comprises obtaining (101) a deformable medical stent (21) in a substantially planar shape, in which the deformable medical stent is adapted for being deployed in a substantially cylindrical shape in the body. The method also comprises attaching (104) a deformable electronic circuit (22) onto the deformable medical stent in the planar shape thereby forming a deformable hybrid structure. The method also comprises shaping (107) said hybrid structure into the cylindrical shape.

公开(公告)号：US20240285394A1

公开(公告)日：2024-08-29

申请号：US18657219

申请日：2024-05-07

Applicant: IMEC VZW

Inventor： Andres Felipe VASQUEZ QUINTERO

IPC: A61F2/14 ,  G01J1/42 ,  G02C7/04 ,  G02F1/133 ,  G02F1/137 ,  G16H10/60 ,  G16H40/40 ,  G16H40/67

CPC classification number: A61F2/14 ,  G01J1/4204 ,  G02C7/04 ,  G02F1/13318 ,  G02F1/137 ,  G16H10/60 ,  G16H40/40 ,  G16H40/67 ,  A61F2250/001

Abstract: A method for controlling an artificial iris comprises: receiving a measurement of light intensity detected by a sensor on or adjacent to the artificial iris; accessing a user-specific profile based on user calibration for determining one or more user-specific thresholds of light intensity of the user-specific profile, wherein the one or more user-specific thresholds are associated with light intensities for triggering a change of light transmittance through the artificial iris; comparing the received measurement of light intensity to the one or more thresholds in the user-specific profile; and determining, based on said comparing, whether to turn on or turn off one or more concentric rings of liquid crystals of the artificial iris for controlling an amount of light transmitted through the artificial iris.

公开(公告)号：US20240266349A1

公开(公告)日：2024-08-08

申请号：US18433779

申请日：2024-02-06

Applicant: IMEC VZW

Inventor： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

Abstract: This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.