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    METHODS FOR FABRICATING INTEGRATED CIRCUITS
    16.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS 有权
    制作集成电路的方法

    公开(公告)号：US20130244387A1

    公开(公告)日：2013-09-19

    申请号：US13420412

    申请日：2012-03-14

    Applicant: Jin Cho

    Inventor： Jin Cho

    IPC: H01L21/336 ,  H01L21/762

    CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material.

    Abstract translation: 提供了形成半导体器件的方法。 一种方法包括形成覆盖体半导体衬底的第一层。 第二层形成在第一层上。 多个沟槽被蚀刻到第一层和第二层中。 设置在多个沟槽之间的第二层的部分限定多个鳍。 形成在多个翅片上的栅极结构。 蚀刻第一层以在体半导体衬底和多个鳍之间形成间隙。 多个鳍片通过栅极结构至少部分地支撑在与间隙空间相邻的位置。 间隙空间填充绝缘材料。

    Parity generating apparatus and map apparatus for turbo decoding
    17.
    发明授权
    Parity generating apparatus and map apparatus for turbo decoding 有权
    用于turbo解码的奇偶校验生成装置和地图装置

    公开(公告)号：US08539325B2

    公开(公告)日：2013-09-17

    申请号：US12972289

    申请日：2010-12-17

    Applicant: In San Jeon ,  Hyuk Kim ,  Han Jin Cho

    Inventor： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

    IPC: G06F11/00

    CPC classification number: H03M13/6525 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927

    Abstract: An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

    Abstract translation: 提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。 用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵 编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。

    Information storage device with domain wall moving unit and magneto-resistive device magnetization arrangement
    18.
    发明授权
    Information storage device with domain wall moving unit and magneto-resistive device magnetization arrangement 有权
    具有域壁移动单元和磁阻装置磁化布置的信息存储装置

    公开(公告)号：US08537506B2

    公开(公告)日：2013-09-17

    申请号：US12801712

    申请日：2010-06-22

    Applicant: Ji-young Bae ,  Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pi ,  Jin-seong Heo

    Inventor： Ji-young Bae ,  Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Ung-hwan Pi ,  Jin-seong Heo

    IPC: G11B5/39

    CPC classification number: G01R33/093 ,  B82Y25/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C19/0808 ,  H01L43/08

    Abstract: An information storage device includes a magnetic track and a magnetic domain wall moving unit. The magnetic track has a plurality of magnetic domains and a magnetic domain wall between each pair of adjacent magnetic domains. The magnetic domain wall moving unit is configured to move at least the magnetic domain wall. The information storage device further includes a magneto-resistive device configured to read information recorded on the magnetic track. The magneto-resistive device includes a pinned layer, a free layer and a separation layer arranged there between. The pinned layer has a fixed magnetization direction. The free layer is disposed between the pinned layer and the magnetic track, and has a magnetization easy axis, which is non-parallel to the magnetization direction of the pinned layer.

    Abstract translation: 信息存储装置包括磁道和磁畴壁移动单元。 磁道在每对相邻磁畴之间具有多个磁畴和磁畴壁。 磁畴壁移动单元构造成至少移动磁畴壁。 信息存储装置还包括被配置为读取记录在磁道上的信息的磁阻装置。 磁阻装置包括钉扎层，自由层和布置在其间的分离层。 被钉扎层具有固定的磁化方向。 自由层设置在被钉扎层和磁迹之间，并且具有与被钉扎层的磁化方向不平行的易磁化轴。

    SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS
    19.
    发明申请
    SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS 有权
    具有接触电介质的半导体器件及相关制造方法

    公开(公告)号：US20130175583A1

    公开(公告)日：2013-07-11

    申请号：US13345388

    申请日：2012-01-06

    Applicant: Lei Yuan ,  Jin Cho ,  Jongwook Kye

    Inventor： Lei Yuan ,  Jin Cho ,  Jongwook Kye

    IPC: H01L29/78 ,  H01L21/768

    CPC classification number: H01L29/4232 ,  H01L21/76834 ,  H01L21/76888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.

    Abstract translation: 提供半导体器件结构的制造方法。 制造半导体器件结构的一种方法包括形成覆盖形成在半导体衬底中的掺杂区域的第一介电材料的第一层，形成电连接到第一层内的掺杂区域的第一导电接触层， 第一导电接触，形成覆盖在电介质盖上的第二电介质材料的第二层和覆盖在半导体衬底上的栅极结构，以及形成电连接到第二层内的栅极结构的第二导电接触。

    SEMICONDUCTOR DEVICE INCLUDING GROUP III-V BARRIER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING GROUP III-V BARRIER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
    包括III-V族阻挡层的半导体器件及制造半导体器件的方法

    公开(公告)号：US20130119347A1

    公开(公告)日：2013-05-16

    申请号：US13611127

    申请日：2012-09-12

    Applicant: Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

    Inventor： Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

    IPC: H01L21/335 ,  H01L29/775

    CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

    Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

    Abstract translation: 一种包括III-V族阻挡层的半导体器件和制造半导体器件的方法，所述半导体器件包括：衬底，形成为在衬底上间隔开的绝缘层，用于填充所述衬底之间的空间的III-V族材料层 所述绝缘层具有比所述绝缘层突出的部分，用于覆盖所述III-V族材料层的所述突出部分的侧表面和上表面的阻挡层，并且具有比所述III-V族材料的带隙大的带隙 层，用于覆盖势垒层的表面的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，以及与栅电极分开形成的源极和漏极。 III-V族材料层的总体组成是均匀的。 阻挡层可以包括用于形成量子阱的III-V族材料。

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