公开(公告)号：US20120274489A1

公开(公告)日：2012-11-01

申请号：US13096908

申请日：2011-04-28

Applicant: Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

Inventor： Soon-Jyh CHANG ,  Guan-Ying Huang ,  Chun-Cheng LIU ,  CHUNG-MING HUANG ,  Jin-Fu LIN ,  Chih-Haur HUANG

IPC: H03M1/00

CPC classification number: H03M1/462 ,  H03M1/466

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window. The SAR controller decodes the outputs of the first and second coarse comparators and the fine comparator to obtain a converted output of the SAR ADC.

Abstract translation: 公开了逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 第一和第二电容器DAC分别接收第一和第二输入信号。 第一粗略比较器将第一电容器DAC的输出与窗口参考电压进行比较，第二粗略比较器将第二电容器DAC的输出与窗口参考电压进行比较，并且精细比较器将第一电容器DAC的输出与 第二电容DAC的输出。 SAR控制器接收第一和第二粗略比较器的输出，以确定第一和第二电容器DAC的输出是否在由窗口参考电压确定的预测窗口内。 当第一电容器DAC和第二电容器DAC的输出被确定为在预测窗口内时，SAR控制器绕过SAR ADC的至少一个模数转换阶段。 SAR控制器解码第一和第二粗略比较器和精细比较器的输出，以获得SAR ADC的转换输出。

公开(公告)号：US07724063B1

公开(公告)日：2010-05-25

申请号：US12326854

申请日：2008-12-02

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03F1/02

CPC classification number: H03F3/005 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45654 ,  H03F2200/78 ,  H03F2203/45136 ,  H03F2203/45404 ,  H03F2203/45648

Abstract: A pseudo-differential switched-capacitor circuit using integrator-based common-mode stabilization technique is disclosed. A pseudo-differential switched-capacitor circuit with the differential floating sampling (DFS) technique has a common-mode gain value of one (1). An integrator is electrically coupled to the differential positive/negative outputs of the DFS circuit, and the integrator feeds back integrator output to the DFS circuit by detecting common-mode voltage disturbance at the differential positive output (Vout+) and negative output (Vout−), thereby stabilizing output common-mode level of the differential positive output (Vout+) and negative output (Vout−) at a desirable level.

Abstract translation: 公开了一种使用基于积分器的共模稳定技术的伪差分开关电容器电路。 具有差分浮动采样（DFS）技术的伪差分开关电容电路具有1（1）的共模增益值。 积分器电耦合到DFS电路的差分正/负输出，积分器通过检测差分正输出（Vout +）和负输出（Vout-）的共模电压干扰，将积分器输出反馈到DFS电路。 从而将差分正输出（Vout +）和负输出（Vout-）的输出共模电平稳定在理想水平。

公开(公告)号：US08299837B1

公开(公告)日：2012-10-30

申请号：US13211292

申请日：2011-08-16

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: G06F7/64

CPC classification number: H03F3/005

Abstract: A pseudo-differential switched-capacitor circuit, which can be applied to various signal processing circuits, employs a floating sampling technique and an integrator feedback loop for isolating a common mode voltage disturbance and restraining a charge injection effect. The pseudo-differential switched-capacitor circuit includes a differential floating sampling circuit that has a pseudo-differential architecture, and an integrator for reducing the charge injection effect within the differential floating sampling circuit.

Abstract translation: 可以应用于各种信号处理电路的伪差分开关电容电路采用浮动采样技术和积分器反馈回路，用于隔离共模电压扰动并抑制电荷注入效应。 伪差分开关电容电路包括具有伪差分架构的差分浮动采样电路和用于降低差分浮动采样电路内的电荷注入效应的积分器。

公开(公告)号：US20120112944A1

公开(公告)日：2012-05-10

申请号：US12941510

申请日：2010-11-08

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin

IPC: H03M1/66

CPC classification number: H03M1/0653 ,  H03M1/806

Abstract: The present invention is directed to a multiplying digital-to-analog converter (MDAC) and its method. First ends of capacitors are electrically coupled to an inverting input node of an amplifier, wherein two of the capacitors are alternatively configured as a feedback capacitor. Each capacitor is composed of at least two sub-capacitors. Second ends of capacitors are electrically coupled to an input signal via a number of sampling switches, and the second ends of the capacitors are electrically coupled to DAC voltages respectively via a number of amplifying switches. A sorting circuit is configured to sort the sub-capacitors, wherein the sorted sub-capacitors are then paired in a manner such that variance of mismatch among the sub-capacitors is thus averaged.

Abstract translation: 本发明涉及一种乘法数模转换器（MDAC）及其方法。 电容器的第一端电耦合到放大器的反相输入节点，其中两个电容器被配置为反馈电容器。 每个电容器由至少两个子电容器组成。 电容器的第二端通过多个采样开关电耦合到输入信号，并且电容器的第二端分别经由多个放大开关电耦合到DAC电压。 排序电路被配置为对子电容器进行排序，其中分选的子电容器然后被配对，使得子电容器之间的失配的变化因此被平均化。

公开(公告)号：US20100085227A1

公开(公告)日：2010-04-08

申请号：US12247186

申请日：2008-10-07

Applicant: Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

Inventor： Soon-Jyh Chang ,  Jin-Fu Lin ,  Chih-Haur Huang

IPC: H03M1/10

CPC classification number: H03M1/1225 ,  H03M1/0695 ,  H03M1/162 ,  H03M1/164 ,  H03M1/40 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) for pipelined ADCs or cyclic ADCs is disclosed. The ADC includes at least one pair of two stages connected in series, and the two stages have different bits of resolution. An amplifier is shared by the pair of two stages such that the two stages operate in an interleaved manner. Accordingly, this stage-resolution scalable opamp-sharing technique is adaptable for pipelined ADC or cyclic ADC, which substantially reduces power consumption and increases operating speed.

Abstract translation: 公开了一种用于流水线ADC或循环ADC的模数转换器（ADC）。 ADC包括串联连接的至少一对两级，两级具有不同的分辨率。 放大器由一对两个级共享，使得两个级以交错方式操作。 因此，这种阶段分辨率可扩展的运算放大器共享技术适用于流水线ADC或循环ADC，这大大降低了功耗并提高了运行速度。

公开(公告)号：US20070066085A1

公开(公告)日：2007-03-22

申请号：US11162726

申请日：2005-09-21

Applicant: Hsien-Che Teng ,  June-Hung Wu ,  Jin-Fu Lin

Inventor： Hsien-Che Teng ,  June-Hung Wu ,  Jin-Fu Lin

IPC: H01L21/469

CPC classification number: H01L21/76801 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/31608

Abstract: A method of fabricating a dielectric layer is described. A twelve-inch wafer having at least three metallic layers thereon is provided. A dielectric layer is formed over the twelve-inch wafer by performing a high-density plasma process. The high-density plasma process includes applying a total bias radio frequency (RF) power and a total source radio frequency (RF) power. Furthermore, the ratio between the total bias RF power and the total source RF power is about 0.7 to 2.5.

Abstract translation: 描述制造介电层的方法。 提供其上具有至少三个金属层的十二英寸晶片。 通过执行高密度等离子体工艺在十二英寸晶片上形成电介质层。 高密度等离子体处理包括施加总偏置射频（RF）功率和总源射频（RF）功率。 此外，总偏置RF功率和总源RF功率之间的比率为约0.7至2.5。

公开(公告)号：US08570206B1

公开(公告)日：2013-10-29

申请号：US13455515

申请日：2012-04-25

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/34

CPC classification number: H03M1/144

Abstract: A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.

Abstract translation: 主数字模拟转换器（DAC）接收至少一个输入并产生经调整的输入。 SAR单元基于接收经调整的输入的比较单元的比较输出产生用于控制主DAC的代码。 参考发生器在产生的代码的控制下产生至少一个参考电压，然后在每个相应周期中转发给比较单元，用于定义每个周期的搜索范围，其中后者的参考电压的绝对值 周期小于前一周期的参考电压，使得后一周期的搜索范围小于前一周期的搜索范围，并且所有周期的搜索范围以基极电压为中心。

公开(公告)号：US08502713B1

公开(公告)日：2013-08-06

申请号：US13470701

申请日：2012-05-14

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/06

CPC classification number: H03M1/0607 ,  H03M1/0695 ,  H03M1/167 ,  H03M1/44

Abstract: A method for correcting a voltage offset influence of a pipelined analog to digital converter is disclosed, in which the method generates a first stage code and a first output voltage according to a first input voltage, generates a second stage code according to the first output voltage, generates a check code according to the first output voltage, determines a first correction code by referring to the first stage code and the check code, and corrects the first stage code with the first correction code when the first stage code is different from the first correction code.

Abstract translation: 公开了一种用于校正流水线模数转换器的电压偏移影响的方法，其中该方法根据第一输入电压产生第一级代码和第一输出电压，根据第一输出电压产生第二级代码 根据第一输出电压生成检查码，通过参照第一级代码和校验码确定第一校正码，并且当第一级代码与第一级代码不同于第一级代码时，用第一校正码校正第一级代码 校正码。

公开(公告)号：US20130076554A1

公开(公告)日：2013-03-28

申请号：US13240806

申请日：2011-09-22

Applicant: YUAN-KAI CHU ,  Jin-Fu LIN

Inventor： YUAN-KAI CHU ,  Jin-Fu LIN

IPC: H03M1/38 ,  H03M1/12

CPC classification number: H03M1/14

Abstract: A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators.

Abstract translation: 用于在转换阶段将模拟输入转换成N位数字输出的SAR ADC包括：三个比较器，每两个电容器子阵列分别耦合到三个比较器，其中使用两个电容器子阵列 用于对模拟输入进行采样并为相应的比较器提供两个输入; 以及耦合到三个比较器和三个电容器阵列的SAR逻辑，用于在每个转换子相中，将每个电容器子阵列的两个选定的电容器耦合到一组确定的参考电平，耦合两个选择的电容器 在前一转换子阶段中，将每个电容器子阵列转换成基于在前一转换子相中从三个比较器输出的一组数据而获得的一组调整参考电平，然后产生N位的两位， 通过对从三个比较器输出的一组数据进行编码来进行位数字输出。

公开(公告)号：US08400343B1

公开(公告)日：2013-03-19

申请号：US13276287

申请日：2011-10-18

Applicant: Jin-Fu Lin

Inventor： Jin-Fu Lin

IPC: H03M1/38

CPC classification number: H03M1/14 ,  H03M1/164 ,  H03M1/468

Abstract: A stage of a pipeline analog-to-digital converter (ADC) is provided according to embodiments of the present invention. The stage of the present invention has double-amplifier architecture and uses level-shifting technique to generate a residue of the stage. The amplifiers of the stage are implemented in two different split paths, thereby to generate a relatively coarse amplification result and a relative fine amplification result. The relatively coarse amplification result is used to level-shift the output level of the amplifier. As a result, the stage of the present invention can have a correct residual by using amplifiers of moderate quality.

Abstract translation: 根据本发明的实施例提供了一个流水线模数转换器（ADC）的级。 本发明的阶段具有双放大器架构，并且使用电平转换技术来产生阶段的残留。 级的放大器以两个不同的分离路径实现，从而产生相对粗略的放大结果和相对精细的放大结果。 相对粗略的放大结果用于对放大器的输出电平进行电平移位。 结果，通过使用中等质量的放大器，本发明的阶段可以具有正确的残差。