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    Common memory device for variable device width and scalable pre-fetch and page size
    14.
    发明授权
    Common memory device for variable device width and scalable pre-fetch and page size 有权
    用于可变设备宽度和可扩展预取和页面大小的通用存储设备

    公开(公告)号：US07957216B2

    公开(公告)日：2011-06-07

    申请号：US12241192

    申请日：2008-09-30

    Applicant: Kuljit S. Bains ,  John Halbert

    Inventor： Kuljit S. Bains ,  John Halbert

    IPC: G11C8/00

    CPC classification number: G11C8/12 ,  G11C7/1021 ,  G11C7/1045 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/108

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a number of modes including, for example, a x4 mode, a x8 mode, and a x16 mode. The page size provided by the DRAM may vary depending on the mode of the DRAM. In some embodiments, the amount of data pre-fetched by the DRAM also varies depending on the mode of the DRAM.

    Abstract translation: 本发明的实施例通常涉及用于可变设备宽度和可缩放预取和页面大小的公共存储器设备的系统，方法和设备。 在一些实施例中，公共存储器件（例如DRAM）可以以包括例如x4模式，x8模式和x16模式在内的多种模式中的任何一种工作。 由DRAM提供的页面大小可以根据DRAM的模式而变化。 在一些实施例中，由DRAM预取的数据量也根据DRAM的模式而变化。

    Temperature determination and communication for multiple devices of a memory module
    15.
    发明授权
    Temperature determination and communication for multiple devices of a memory module 有权
    存储器模块的多个器件的温度测定和通信

    公开(公告)号：US07450456B2

    公开(公告)日：2008-11-11

    申请号：US11801909

    申请日：2007-05-10

    Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

    Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

    IPC: G11C7/04 ,  G11C5/06

    CPC classification number: G11C7/04 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3089 ,  G11C5/04 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1063

    Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

    Abstract translation: 确定存储器模块的多个设备的温度。 在一个示例中，存储器模块包括印刷电路板，印刷电路板上的多个存储器芯片，每个芯片包含多个存储单元和热传感器，以及印刷电路板上的多路复用器，独立于存储器芯片 ，耦合到每个热传感器。 电流源耦合到多路复用器以向每个热传感器提供电流，并且电压检测器耦合到多路复用器以在施加电流时检测来自每个热传感器的电压。 温度电路耦合到电压检测器，以基于检测到的电压来确定每个存储器芯片的温度。

    Multiported memory with ports mapped to bank sets
    16.
    发明申请
    Multiported memory with ports mapped to bank sets 审中-公开
    多端口存储器，端口映射到银行集

    公开(公告)号：US20070150667A1

    公开(公告)日：2007-06-28

    申请号：US11317757

    申请日：2005-12-23

    Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

    Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

    IPC: G06F13/28

    CPC classification number: G06F13/1684

    Abstract: In some embodiments, a chip includes first and second bank sets, a first data port mapped to the first bank set, and a second data port mapped to the second bank set. Other embodiments are described.

    Abstract translation: 在一些实施例中，芯片包括第一和第二组组，映射到第一组组的第一数据端口和映射到第二组组的第二数据端口。 描述其他实施例。

    Memory having swizzled signal lines
    17.
    发明申请
    Memory having swizzled signal lines 审中-公开
    存储器有信号线

    公开(公告)号：US20070005836A1

    公开(公告)日：2007-01-04

    申请号：US11148160

    申请日：2005-06-07

    Applicant: Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

    Inventor： Sandeep Jain ,  George Vergis ,  John Halbert ,  Nilesh Shah

    IPC: G06F13/38

    CPC classification number: G06F13/4013 ,  G11C5/06 ,  G11C7/04 ,  G11C7/1006 ,  G11C8/20

    Abstract: Swizzle information for signal lines on a memory component may be stored on the memory component. The swizzle information may be transmitted to a memory controller which may include logic to receive the swizzle information which is then used to deswizzle data received from the memory component. Data may be transmitted from a memory device to a memory controller in a format that is tolerant of swizzling on signal lines between the device and the controller. The format may include codes having unique of numbers of values. Data may be sent in multi-code bursts that divide a data range into progressively smaller ranges. Other embodiments are described and claimed.

    Abstract translation: 存储器组件上的信号线的交换信息可以存储在存储器组件上。 交换信息可以被发送到存储器控制器，存储器控制器可以包括用于接收转移信息的逻辑，然后用于去除从存储器组件接收的数据。 数据可以以容许在设备和控制器之间的信号线上进行转换的格式从存储器件发送到存储器控制器。 该格式可以包括具有唯一值的值的代码。 可以以将多个数字范围分割成逐渐变小的多码脉冲串来发送数据。 描述和要求保护其他实施例。

    Techniques to map cache data to memory arrays
    18.
    发明授权
    Techniques to map cache data to memory arrays 失效
    将缓存数据映射到存储器阵列的技术

    公开(公告)号：US06954822B2

    公开(公告)日：2005-10-11

    申请号：US10211680

    申请日：2002-08-02

    Applicant: Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    Inventor： Kuljit S. Bains ,  Herbert Hum ,  John Halbert

    IPC: G06F12/08 ,  G06F12/00

    CPC classification number: G06F12/0864 ,  G06F12/0893 ,  G06F2212/3042

    Abstract: Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.

    Abstract translation: 将缓存内容映射到存储器阵列的方法和装置。 在一个实施例中，一种装置包括处理器部分和将高速缓存路径映射到存储体的高速缓存控制器。 在一个实施例中，每个存储体包括来自一个缓存方式的数据。 在另一个实施例中，每个存储体包括来自每个方式的数据。 在另一个实施例中，存储器阵列组包含对应于顺序高速缓存线的数据。

    Memory buffer device integrating ECC
    20.
    发明申请
    Memory buffer device integrating ECC 有权
    集成ECC的内存缓冲设备

    公开(公告)号：US20050081085A1

    公开(公告)日：2005-04-14

    申请号：US10674320

    申请日：2003-09-29

    Applicant: Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert

    Inventor： Robert Ellis ,  Kuljit Bains ,  Chris Freeman ,  John Halbert

    IPC: G06F11/00 ,  G06F11/10

    CPC classification number: G06F11/1044

    Abstract: Apparatus and method to carry out checks for memory errors within a memory device independently of a memory controller during times when there is no activity on a memory bus coupling the memory device to the memory controller that involves the memory device.

    Abstract translation: 在存储器总线上没有活动的情况下，与存储器控制器独立地对存储器件内的存储器错误执行检查的装置和方法，该存储器总线将存储器装置耦合到涉及存储器件的存储器控​​制器。

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