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    Methods of forming integrated circuit devices having metal interconnect structures therein
    11.
    发明授权
    Methods of forming integrated circuit devices having metal interconnect structures therein 失效
    形成其中具有金属互连结构的集成电路器件的方法

    公开(公告)号：US07435673B2

    公开(公告)日：2008-10-14

    申请号：US11237987

    申请日：2005-09-28

    Applicant: Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

    Inventor： Kyoung Woo Lee ,  Ja-Hum Ku ,  Duk Ho Hong ,  Wan Jae Park

    IPC: H01L21/4763

    CPC classification number: H01L21/7684 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76877

    Abstract: Methods of forming metal interconnect structures include forming a first electrically insulating layer on a semiconductor substrate and forming a second electrically insulating layer on the first electrically insulating layer. The second and first electrically insulating layers are selectively etched in sequence to define a contact hole therein. A first metal layer (e.g., tungsten) is deposited. This first metal layer extends on the second electrically insulating layer and into the contact hole. The first metal layer is then patterned to expose the second electrically insulating layer. The second electrically insulating layer is selectively etched for a sufficient duration to expose the first electrically insulating layer and expose a metal plug within the contact hole. This selective etching step is performed using the patterned first metal layer as an etching mask. A seam within the exposed metal plug is then filled with an electrically conductive filler material (e.g., CoWP). A second metal layer is then formed on the exposed metal plug containing the electrically conductive filler material.

    Abstract translation: 形成金属互连结构的方法包括在半导体衬底上形成第一电绝缘层，并在第一电绝缘层上形成第二电绝缘层。 依次选择性地蚀刻第二和第一电绝缘层以在其中限定接触孔。 沉积第一金属层（例如钨）。 该第一金属层在第二电绝缘层上延伸并进入接触孔。 然后将第一金属层图案化以暴露第二电绝缘层。 选择性地蚀刻第二电绝缘层足够的持续时间以暴露第一电绝缘层并在接触孔内露出金属插塞。 使用图案化的第一金属层作为蚀刻掩模来执行该选择性蚀刻步骤。 暴露的金属插头内的接缝然后用导电填充材料（例如，CoWP）填充。 然后在暴露的包含导电填料的金属塞上形成第二金属层。

    Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating
    12.
    发明授权
    Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating 失效
    金属 - 绝缘体 - 金属电容器的双镶嵌互连和制造方法

    公开(公告)号：US07399700B2

    公开(公告)日：2008-07-15

    申请号：US11897417

    申请日：2007-08-30

    Applicant: Kyoung-woo Lee ,  Soo-geun Lee

    Inventor： Kyoung-woo Lee ,  Soo-geun Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

    Abstract translation: 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

    Methods of forming copper vias with argon sputtering etching in dual damascene processes
    15.
    发明申请
    Methods of forming copper vias with argon sputtering etching in dual damascene processes 审中-公开
    在双镶嵌工艺中用氩气溅射蚀刻形成铜通孔的方法

    公开(公告)号：US20070202689A1

    公开(公告)日：2007-08-30

    申请号：US11363070

    申请日：2006-02-27

    Applicant: Seung-Man Choi ,  Kyoung-Woo Lee

    Inventor： Seung-Man Choi ,  Kyoung-Woo Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76814 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849

    Abstract: A method of forming a via using a dual damascene process can be provided by forming a via in an insulating layer above a lower level copper interconnect and etching into a surface of the lower level copper interconnect in the via using Argon (Ar) sputtering. Then a trench is formed above a lower portion of the via and an upper level copper interconnect is formed in the lower portion of the via and in the trench using a dual damascene process.

    Abstract translation: 可以通过在下层铜互连上方的绝缘层中形成通孔并使用氩（Ar）溅射在通孔中蚀刻到下层铜互连的表面中来提供使用双镶嵌工艺形成通孔的方法。 然后在通孔的下部形成沟槽，并且使用双镶嵌工艺在通孔的下部和沟槽中形成上层铜互连。

    Dual damascene process
    18.
    发明授权
    Dual damascene process 有权
    双镶嵌工艺

    公开(公告)号：US07033944B2

    公开(公告)日：2006-04-25

    申请号：US10654770

    申请日：2003-09-04

    Applicant: Wan-Jae Park ,  Il-Goo Kim ,  Sang-Rok Hah ,  Kyoung-Woo Lee

    Inventor： Wan-Jae Park ,  Il-Goo Kim ,  Sang-Rok Hah ,  Kyoung-Woo Lee

    IPC: H01L21/302

    CPC classification number: H01L21/76808

    Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

    Abstract translation: 公开了一种双镶嵌工艺。 根据本发明的双镶嵌工艺，通过金属间电介质层的第一凹陷区域填充有底部保护层，同时蚀刻底部保护层和金属间电介质层，以形成第二凹陷区域，该凹陷区域具有 通过使用蚀刻气体相对于底部保护层选择性地蚀刻金属间电介质层，比第一凹陷区域上的第一凹陷区域更浅的深度和更宽的宽度。 换句话说，相对于底部保护层的蚀刻选择比，金属间电介质层优选为约0.5至约1.5。 因此，可以形成双重镶嵌结构而不形成副产物或氧化物栅栏。

    Method of forming metal interconnection layer of semiconductor device
    19.
    发明申请
    Method of forming metal interconnection layer of semiconductor device 有权
    形成半导体器件金属互连层的方法

    公开(公告)号：US20050037605A1

    公开(公告)日：2005-02-17

    申请号：US10888577

    申请日：2004-07-09

    Applicant: Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

    Inventor： Il-Goo Kim ,  Sang-Rok Hah ,  Sae-il Son ,  Kyoung-Woo Lee

    IPC: H01L21/768 ,  H01L21/4763

    CPC classification number: H01L21/76808 ,  H01L21/76813

    Abstract: Various methods are provided for forming metal interconnection layers of semiconductor devices. One exemplary method for forming a metal interconnection layer of a semiconductor device includes forming an interlayer dielectric layer on a substrate, forming a hard mask layer on the interlayer dielectric layer, wherein the hard mask layer serves as an anti-reflection layer, depositing and patterning a first photoresist layer to form a first photoresist pattern on the hard mask layer, forming a partial via hole in the interlayer dielectric layer by etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask, removing the first photoresist pattern, depositing a second photoresist layer to fill the partial via hole with photoresist material and patterning the second photoresist layer to form a second photoresist pattern that defines a trench interconnection area which overlaps at least portion of the partial via hole, etching the hard mask layer using the second photoresist pattern as an etching mask to form a hard mask pattern, completely removing the second photoresist pattern and the photoresist material in the partial via hole, etching the interlayer dielectric layer using the hard mask pattern as an etching mask to form the trench interconnection area and to extend the partial via hole to form a full via hole, and filling the full via hole and the trench interconnection area with a conductive material.

    Abstract translation: 提供用于形成半导体器件的金属互连层的各种方法。 用于形成半导体器件的金属互连层的一种示例性方法包括在衬底上形成层间电介质层，在层间介质层上形成硬掩模层，其中硬掩模层用作抗反射层，沉积和图案化 第一光致抗蚀剂层，以在硬掩模层上形成第一光致抗蚀剂图案，通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，在层间电介质层中形成部分通孔， 沉积第二光致抗蚀剂层以用光致抗蚀剂材料填充部分通孔并且图案化第二光致抗蚀剂层以形成第二光致抗蚀剂图案，其限定与部分通孔的至少部分重叠的沟槽互连区域，蚀刻硬掩模 层，使用第二光致抗蚀剂图案作为蚀刻掩模以形成硬掩模图案 n，完全去除部分通孔中的第二光致抗蚀剂图案和光致抗蚀剂材料，使用硬掩模图案作为蚀刻掩模蚀刻层间介电层，以形成沟槽互连区域并延伸部分通孔以形成完整通孔 并且用导电材料填充整个通孔和沟槽互连区域。

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