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    Method for forming metal wiring layer of semiconductor device
    2.
    发明授权
    Method for forming metal wiring layer of semiconductor device 有权
    用于形成半导体器件的金属布线层的方法

    公开(公告)号：US06815331B2

    公开(公告)日：2004-11-09

    申请号：US10392710

    申请日：2003-03-20

    申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    IPC分类号： H01L214163

    CPC分类号： H01L21/76808 ,  H01L21/76813

    摘要： Methods for forming a metal wiring layer in a semiconductor device using a dual damascene process. In one aspect, a method for forming metal wiring in a semiconductor device comprises: forming a stopper layer on a semiconductor substrate that has a conductive layer formed thereon; forming an interlayer dielectric layer on the stopper layer; forming a hard mask layer on the interlayer dielectric layer; forming a first photoresist pattern on the hard mask layer, the first photoresist pattern having a first opening corresponding to the conductive layer; etching the hard mask layer and the interlayer dielectric layer using the first photoresist pattern as an etching mask to form a via hole in the interlayer dielectric layer through which a portion of the stopper layer is exposed; removing the first photoresist pattern; filling the via hole with an intermediary material layer; etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region, wherein the hard mask pattern comprises a second opening that overlaps the entire via hole or at least a portion of the via hole; removing the intermediary material layer from the via hole; forming the wiring region by etching a portion of the interlayer dielectric layer using the hard mask pattern as an etching mask; removing a portion of the stopper layer exposed by the via hole; and filling the via hole and the wiring region with a conductive material.

    摘要翻译： 使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 一方面，在半导体器件中形成金属布线的方法包括：在其上形成有导电层的半导体衬底上形成阻挡层; 在所述阻挡层上形成层间绝缘层; 在所述层间介质层上形成硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂图案，所述第一光致抗蚀剂图案具有对应于所述导电层的第一开口; 使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻硬掩模层和层间电介质层，以在阻挡层的一部分暴露的层间绝缘层中形成通孔; 去除第一光致抗蚀剂图案; 用中间材料层填充通孔; 蚀刻硬掩模层的一部分以形成限定布线区域的硬掩模图案，其中硬掩模图案包括与整个通孔或通孔的至少一部分重叠的第二开口; 从所述通孔中去除所述中间材料层; 通过使用硬掩模图案作为蚀刻掩模蚀刻层间电介质层的一部分来形成布线区域; 去除由通孔露出的阻挡层的一部分; 以及用导电材料填充所述通孔和所述布线区域。

    Method for forming metal wiring layer of semiconductor device
    3.
    发明授权
    Method for forming metal wiring layer of semiconductor device 有权
    用于形成半导体器件的金属布线层的方法

    公开(公告)号：US06861347B2

    公开(公告)日：2005-03-01

    申请号：US10114274

    申请日：2002-04-02

    申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

    摘要： A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.

    摘要翻译： 提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。 包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。 使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。 去除第一光致抗蚀剂图案。 在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。 在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。 使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。 同时去除第二光致抗蚀剂图案和有机材料层。 通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

    Method of manufacturing interconnection line in semiconductor device
    4.
    发明授权
    Method of manufacturing interconnection line in semiconductor device 有权
    在半导体器件中制造互连线的方法

    公开(公告)号：US06828229B2

    公开(公告)日：2004-12-07

    申请号：US10081661

    申请日：2002-02-22

    申请人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

    发明人： Soo-geun Lee ,  Hong-jae Shin ,  Kyoung-woo Lee ,  Jae-hak Kim

    IPC分类号： H01L214763

    CPC分类号： H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

    摘要： A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

    摘要翻译： 提供了一种在半导体器件中形成互连线的方法。 在形成在半导体衬底上的下导电层上形成第一蚀刻阻挡层。 在第一蚀刻停止件上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻停止件上形成第二层间绝缘层。 使用第一蚀刻停止器作为蚀刻停止点，依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下导电层对准的通孔。 形成保护层以保护暴露在通孔底部的第一蚀刻终止部分。 使用第二蚀刻停止器蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点，以形成连接到通孔的沟槽。 保护层被去除。 位于通孔底部的第一蚀刻停止部分被去除。 形成填充通孔和沟槽并与下导电层电连接的上导电层。

    Method of manufacturing semiconductor device including ultra low dielectric constant layer
    6.
    发明申请
    Method of manufacturing semiconductor device including ultra low dielectric constant layer 审中-公开
    包括超低介电常数层的半导体器件的制造方法

    公开(公告)号：US20090280637A1

    公开(公告)日：2009-11-12

    申请号：US12453326

    申请日：2009-05-07

    申请人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

    发明人： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Jae-ouk Choo

    IPC分类号： H01L21/768

    CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02362 ,  H01L21/31695

    摘要： Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法在形成金属线之前和之后，在包含在低电介质层中的多个不同的致孔剂上采用多步除去，从而有助于形成超低介电常数层，该超低介电常数层用作金属线之间的绝缘层 半导体器件。 该方法可以包括在衬底上形成层间电介质层，在层间电介质层中形成多个致孔剂，去除层间电介质层中的多个致孔剂的一部分，以在层间电介质层中形成多个第一孔， 形成其中形成有多个第一孔的布线图案，并且除去多个致孔剂中剩余的孔隙原，以在层间电介质层中形成多个第二孔。

    Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods
    8.
    发明申请
    Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods 审中-公开
    在使用这种方法制造的半导体器件和半导体器件中制造镶嵌互连线的方法

    公开(公告)号：US20070059923A1

    公开(公告)日：2007-03-15

    申请号：US11445458

    申请日：2006-06-02

    申请人： Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

    发明人： Hyo-jong Lee ,  Ui-hyoung Lee ,  Hong-jae Shin ,  Nae-in Lee ,  Soo-geun Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76885 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76843

    摘要： Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.

    摘要翻译： 在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。 该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔 保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽 ，并填充沟槽以制造连接到通孔的镶嵌互连线。

    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    9.
    发明授权
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US07446033B2

    公开(公告)日：2008-11-04

    申请号：US11336905

    申请日：2006-01-23

    申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    10.
    发明申请
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US20060177630A1

    公开(公告)日：2006-08-10

    申请号：US11336905

    申请日：2006-01-23

    申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC分类号： B32B3/04

    CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。