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    NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE
    11.
    发明申请
    NONVOLATILE MEMORY DEVICE, STORAGE SYSTEM HAVING THE SAME, AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE 有权
    非易失性存储器件，具有该存储器件的存储器件，以及驱动非易失性存储器件的方法

    公开(公告)号：US20110080775A1

    公开(公告)日：2011-04-07

    申请号：US12893413

    申请日：2010-09-29

    Applicant: Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

    Inventor： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

    IPC: G11C11/00 ,  G11C7/04

    CPC classification number: G11C8/12 ,  G11C7/04 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5634

    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

    Abstract translation: 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储单元，每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻，温度补偿电路包括一个或多个参考单元，每个参考单元具有对应于一个 或更多的第二电阻分布，以及包括补偿单元和读出放大器的数据读取电路，所述补偿单元适于向感测节点提供补偿电流，所述补偿电流的量基于每个参考单元的电阻而变化， 并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

    Semiconductor device and semiconductor system having the same
    12.
    发明授权
    Semiconductor device and semiconductor system having the same 有权
    半导体器件和具有该半导体器件的半导体系统

    公开(公告)号：US07881145B2

    公开(公告)日：2011-02-01

    申请号：US12453872

    申请日：2009-05-26

    Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    IPC: G11C8/00

    CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

    Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

    Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

    Method of testing PRAM device
    13.
    发明授权
    Method of testing PRAM device 有权
    PRAM设备的测试方法

    公开(公告)号：US07869271B2

    公开(公告)日：2011-01-11

    申请号：US12787571

    申请日：2010-05-26

    Applicant: Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    Inventor： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

    IPC: G11C11/00

    CPC classification number: G11C29/08 ,  G11C13/0004

    Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

    Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

    METHOD OF TESTING PRAM DEVICE
    14.
    发明申请
    METHOD OF TESTING PRAM DEVICE 有权
    测试伪装置的方法

    公开(公告)号：US20100232218A1

    公开(公告)日：2010-09-16

    申请号：US12787571

    申请日：2010-05-26

    Applicant: Chang-Soo LEE ,  Hyung-Rok OH ,  Beak-Hyung CHO ,  Kwang-Jin LEE

    Inventor： Chang-Soo LEE ,  Hyung-Rok OH ,  Beak-Hyung CHO ,  Kwang-Jin LEE

    IPC: G11C11/00 ,  G11C29/00 ,  G11C8/00

    CPC classification number: G11C29/08 ,  G11C13/0004

    Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

    Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

    Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith
    16.
    发明申请
    Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 审中-公开
    具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件

    公开(公告)号：US20100131708A1

    公开(公告)日：2010-05-27

    申请号：US12292896

    申请日：2008-11-28

    Applicant: Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

    Inventor： Joon-Min Park ,  Kwang Jin Lee ,  Beak-Hyung Cho

    IPC: G06F12/00

    CPC classification number: G11C13/0069 ,  G11C15/046 ,  G11C2013/0076

    Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.

    Abstract translation: 在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址 在写缓冲区。 输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。 旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。 如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

    Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices
    18.
    发明申请
    Phase-Change and Resistance-Change Random Access Memory Devices and Related Methods of Performing Burst Mode Operations in Such Memory Devices 有权
    相变和电阻变化随机存取存储器件以及在这种存储器件中执行突发模式操作的相关方法

    公开(公告)号：US20100124102A1

    公开(公告)日：2010-05-20

    申请号：US12582880

    申请日：2009-10-21

    Applicant: Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    Inventor： Kwang-Jin Lee ,  Young-kug Moon ,  Young-pil Kim

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/004 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004

    Abstract: Phase-change and resistance-change random access memory devices are provided which include a phase-change or resistance-change memory cell array and a sense amplifier that is configured to amplify data read from the phase-change memory cell array. These random access memory devices are configured to read data from a first word line of the phase-change or resistance-change memory cell array and to insert a dummy burst in which no data is read when a first boundary crossing occurs during a burst mode operation. Related methods of operating phase-change and/or resistance-change random access memory devices in burst mode are also provided.

    Abstract translation: 提供了相变和电阻变化随机存取存储器件，其包括相变或电阻变化存储单元阵列和被配置为放大从相变存储单元阵列读取的数据的读出放大器。 这些随机存取存储器件被配置为从相变或电阻变化存储单元阵列的第一字线读取数据，并且在突发模式操作期间发生第一边界交叉时插入其中没有读取数据的虚拟脉冲串 。 还提供了以突发模式操作相变和/或电阻变化随机存取存储器件的相关方法。

    Input circuit of a non-volatile semiconductor memory device
    19.
    发明授权
    Input circuit of a non-volatile semiconductor memory device 有权
    非易失性半导体存储器件的输入电路

    公开(公告)号：US07710791B2

    公开(公告)日：2010-05-04

    申请号：US11984145

    申请日：2007-11-14

    Applicant: Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    Inventor： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

    IPC: G11C7/10 ,  G11C8/06 ,  G11C7/22 ,  G11C8/18

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

    Abstract: A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

    Abstract translation: 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

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