公开(公告)号：US06933243B2

公开(公告)日：2005-08-23

申请号：US10279320

申请日：2002-10-23

申请人： Meihua Shen ,  Yan Du ,  Nicolas Gani ,  Oranna Yauw ,  Hakeem M. Oluseyi

发明人： Meihua Shen ,  Yan Du ,  Nicolas Gani ,  Oranna Yauw ,  Hakeem M. Oluseyi

IPC分类号： H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/302

CPC分类号： H01L21/28088 ,  H01L21/32136 ,  H01L29/4966

摘要： Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

摘要翻译： 提供了直接形成在栅极电介质上的蚀刻电极的方法。 在一个方面，提供了一种蚀刻工艺，其包括主蚀刻步骤，软着色步骤和过蚀刻步骤。 在另一方面，描述了一种方法，其包括执行具有良好蚀刻速率均匀性和良好轮廓均匀性的主蚀刻，执行软着色步骤，其中可以确定金属/金属屏障界面，以及执行过蚀刻步骤以选择性地去除 金属屏障，而不会对电介质产生负面影响。 在另一方面，提供了一种方法，其包括用于大量去除电极材料的第一非选择性蚀刻化学品，具有端点能力的第二中间选择性蚀刻化学品，然后选择蚀刻化学物质停止在栅极电介质上。

公开(公告)号：US06566270B1

公开(公告)日：2003-05-20

申请号：US09662677

申请日：2000-09-15

申请人： Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

发明人： Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

IPC分类号： H01L21302

CPC分类号： H01L21/3065

摘要： A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

摘要翻译： 用于处理设置在具有源功率的基板处理室中的基板的方法包括将基板转移到基板处理室中。 通过从源功率系统施加RF能量并将等离子体偏压到衬底，将衬底暴露于由第一蚀刻剂气体形成的等离子体上，在衬底上蚀刻沟槽。 通过在不施加偏置功率或施加最小偏压功率的情况下点燃由包括卤素源的第二蚀刻剂气体在衬底处理室中形成的等离子体而去除附着于衬底处理室的内表面的副产物。 此后，将基板从腔室中取出。 在对腔室进行干洗或湿清洁操作之前，至少用100个蚀刻a沟槽步骤和去除蚀刻副产物步骤处理多个衬底。

公开(公告)号：US10658161B2

公开(公告)日：2020-05-19

申请号：US13174090

申请日：2011-06-30

申请人： Xikun Wang ,  Andrew Nguyen ,  Changhun Lee ,  Xiaoming He ,  Meihua Shen

发明人： Xikun Wang ,  Andrew Nguyen ,  Changhun Lee ,  Xiaoming He ,  Meihua Shen

IPC分类号： H01L21/3213 ,  H01J37/32

摘要： In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.

公开(公告)号：US20120091095A1

公开(公告)日：2012-04-19

申请号：US13174090

申请日：2011-06-30

申请人： Xikun WANG ,  Andrew NGUYEN ,  Changhun LEE ,  Xiaoming HE ,  Meihua SHEN

发明人： Xikun WANG ,  Andrew NGUYEN ,  Changhun LEE ,  Xiaoming HE ,  Meihua SHEN

IPC分类号： C23F1/00 ,  C23F1/08 ,  B05B1/00

摘要： In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.

摘要翻译： 用于原位沉积室涂层的等离子体处理系统的原位低压室清洗和气体喷嘴装置。 用于导体蚀刻应用的某些室清洁实施例包括在低于30mT的压力下进行的基于NF 3的等离子体清洁，以从气体喷嘴孔的内表面去除原位沉积的SiO x涂层。 实施例包括具有足够小的底部孔的气体喷嘴，以减少或防止原位沉积的室涂层在喷嘴孔的内表面上建立SiO x沉积物。

公开(公告)号：US20120088371A1

公开(公告)日：2012-04-12

申请号：US13089374

申请日：2011-04-19

申请人： ALOK RANJAN ,  NICOLAS GANI ,  MEIHUA SHEN ,  ANISUL H. KHAN

发明人： ALOK RANJAN ,  NICOLAS GANI ,  MEIHUA SHEN ,  ANISUL H. KHAN

IPC分类号： H01L21/3065

CPC分类号： H01L21/3065 ,  H01J37/32082 ,  H01J37/32697 ,  H01J2237/334 ,  H01L21/31116 ,  H01L21/32136

摘要： Methods for etching substrates using a pulsed DC voltage are provided herein. In some embodiments, a method for method for etching a substrate disposed on a substrate support within a process chamber may include providing a process gas to the process chamber; forming a plasma from the process gas; applying a pulsed DC voltage to a first electrode disposed within the process chamber; and etching the substrate while applying the pulsed DC voltage.

摘要翻译： 本文提供了使用脉冲DC电压蚀刻基板的方法。 在一些实施例中，用于蚀刻设置在处理室内的衬底支撑件上的衬底的方法的方法可包括向处理室提供工艺气体; 从工艺气体形成等离子体; 向设置在处理室内的第一电极施加脉冲DC电压; 并在施加脉冲DC电压的同时刻蚀衬底。

公开(公告)号：US20090032880A1

公开(公告)日：2009-02-05

申请号：US11833481

申请日：2007-08-03

申请人： Mark Naoshi Kawaguchi ,  Meihua Shen ,  Hiroki Sasano ,  Rong Chen

发明人： Mark Naoshi Kawaguchi ,  Meihua Shen ,  Hiroki Sasano ,  Rong Chen

IPC分类号： H01L29/94 ,  H01L21/302 ,  H01L21/311

CPC分类号： H01L29/7848 ,  H01L21/3065 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66636

摘要： Methods and apparatuses to etch recesses in a silicon substrate having an isotropic character to undercut a transistor in preparation for a source/drain regrowth. In one embodiment, a cap layer of a first thickness is deposited over a transistor gate stack and spacer structure. The cap layer is then selectively etched in a first region of the substrate, such as a p-MOS region, using a first isotropic plasma etch process and a second anisotropic plasma etch process. In another embodiment, an at least partially isotropic plasma recess etch is performed to provide a recess adjacent to the channel region of the transistor. In a particular embodiment, the plasma etch process provides a recess sidewall that is neither positively sloped nor more than 10 nm re-entrant.

摘要翻译： 蚀刻具有各向同性特征的硅衬底中的凹陷的方法和装置，以切割晶体管以准备源极/漏极再生长。 在一个实施例中，第一厚度的覆盖层沉积在晶体管栅极叠层和间隔结构上。 然后使用第一各向同性等离子体蚀刻工艺和第二各向异性等离子体蚀刻工艺，在衬底的第一区域（例如p-MOS区）中选择性地蚀刻覆盖层。 在另一个实施例中，执行至少部分各向同性等离子体凹陷蚀刻以提供与晶体管的沟道区相邻的凹陷。 在特定实施例中，等离子体蚀刻工艺提供了既不正向倾斜也不超过10nm的凹陷侧壁。

公开(公告)号：US20070202700A1

公开(公告)日：2007-08-30

申请号：US11363789

申请日：2006-02-27

申请人： Uwe Leucke ,  Meihua Shen ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

发明人： Uwe Leucke ,  Meihua Shen ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

IPC分类号： H01L21/302 ,  C23F1/00

CPC分类号： C23F4/00 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

摘要翻译： 在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。 本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。 在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。 在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。 均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面 层。

公开(公告)号：US20070199922A1

公开(公告)日：2007-08-30

申请号：US11363834

申请日：2006-02-27

申请人： Meihua Shen ,  Uwe Leucke ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

发明人： Meihua Shen ,  Uwe Leucke ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

IPC分类号： H01L21/461 ,  B44C1/22 ,  H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/32137 ,  H01L21/76814

摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

公开(公告)号：US20060252265A1

公开(公告)日：2006-11-09

申请号：US11126472

申请日：2005-05-11

申请人： Guangxiang Jin ,  Meihua Shen

发明人： Guangxiang Jin ,  Meihua Shen

IPC分类号： C23F1/00 ,  H01L21/302

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： An apparatus and a method for etching high dielectric constant (high-κ) materials using halogen containing gas and reducing gas chemistries are provided. One embodiment of the method is accomplished by etching a layer using two etch gas chemistries in separate steps. The first etch gas chemistry contain no oxygen containing gas in order to break through etching of the high dielectric constant materials, to dean any residues left from previous polysilicon etch process resulting in less high-κ foot, and also to control silicon recess problem associated with an underlying silicon oxide layer. The second over-etch gas chemistry provides a high etch selectivity for high dielectric constant materials over silicon oxide materials to be combined with low source power to further reduce silicon substrate oxidation problem.

摘要翻译： 提供了使用含卤素气体和还原气体化学物质蚀刻高介电常数（高kappa）材料的设备和方法。 该方法的一个实施方案是通过在单独的步骤中使用两种蚀刻气体化学物质来蚀刻层而实现的。 为了突破高介电常数材料的蚀刻，第一蚀刻气体化学物质不含氧气，以防止从先前的多晶硅蚀刻工艺留下的任何残留物导致较低的高卡宾脚，并且还控制与 底层氧化硅层。 第二种过蚀刻气体化学提供了高氧化硅材料上的高介电常数材料的高蚀刻选择性，以与低源功率组合以进一步减少硅衬底氧化问题。

公开(公告)号：US20060231524A1

公开(公告)日：2006-10-19

申请号：US11422031

申请日：2006-06-02

申请人： Wei Liu ,  Jim He ,  Sang Ahn ,  Meihua Shen ,  Hichem M'Saad ,  Wendy Yeh ,  Christopher Bencher

发明人： Wei Liu ,  Jim He ,  Sang Ahn ,  Meihua Shen ,  Hichem M'Saad ,  Wendy Yeh ,  Christopher Bencher

IPC分类号： C23F1/00 ,  B44C1/22 ,  G03C5/00 ,  H01L21/302 ,  C03C25/68

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/3146

摘要： A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

摘要翻译： 提供蚀刻基板的方法。 蚀刻基板的方法包括使用基板上的双图案化非晶碳层作为硬掩模将图案转印到基板中。 任选地，在将图案转移到基底内之前，将非碳基层沉积在无定形碳层上作为覆盖层。