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公开(公告)号：US09142280B1
公开(公告)日：2015-09-22
申请号：US14452536
申请日：2014-08-06
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4074 , G11C11/4093 , G11C11/4094
CPC分类号： G11C11/40615 , G11C11/4074 , G11C11/4093 , G11C11/4094 , G11C2211/4067
摘要： A circuit for configuring an external memory includes a memory controller, a register, an OR gate, first and second input/output (IO) pads, and pull-up and pull-down resistors. When the circuit is in a high power mode, the memory controller refreshes the external memory by providing reset and clock enable signals to the external memory by way of the first and second IO pads. When the circuit is in a low power mode, the pull-up and pull-down resistors configure the external memory in a self-refresh mode. When the circuit exits the low power mode, the first and second IO pads are powered on. The OR gate receives and provides a control signal output by the register to the external memory by way of the first IO pad, which keeps the external memory in the self-refresh mode.
摘要翻译： 用于配置外部存储器的电路包括存储器控制器，寄存器，或门，第一和第二输入/输出（IO）焊盘以及上拉和下拉电阻。 当电路处于高功率模式时，存储器控制器通过第一和第二IO焊盘向外部存储器提供复位和时钟使能信号来刷新外部存储器。 当电路处于低功耗模式时，上拉和下拉电阻将自身刷新模式下的外部存储器配置。 当电路退出低功耗模式时，第一个和第二个IO焊盘通电。 或门通过第一个IO接口接收寄存器输出的控制信号到外部存储器，保持外部存储器处于自刷新模式。
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公开(公告)号：US08890602B2
公开(公告)日：2014-11-18
申请号：US13743324
申请日：2013-01-16
IPC分类号： H03K3/01
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译： 用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器 ）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。 在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。 分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。
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13.发明授权Power management circuit using two configuration signals to control the power modes of two circuit modules using two crosslinked multiplexers and a level shifter 有权电源管理电路使用两个配置信号来控制两个电路模块的功率模式，使用两个交流多路复用器和电平转换器公开(公告)号：US08762753B2
公开(公告)日：2014-06-24
申请号：US13525347
申请日：2012-06-17
申请人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
发明人： Kumar Abhishek , Manmohan Rana , Samaksh Sinha
CPC分类号： G06F1/3287 , G06F1/3243 , H02J1/08 , H02J9/005 , H02J2001/008 , Y02D10/152 , Y02D50/20
摘要： A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.
摘要翻译： 一种用于管理由核心电源供应到电子电路的电力的电源管理电路。 电子电路包括数字和模拟电路域，并在POWER-ON，RUN和STANDBY模式下工作。 电源管理电路包括主状态机，其与模拟电路域交换握手信号以监视操作模式并产生第一和第二配置信号。 电源管理电路基于第一和第二配置信号启用和禁用模拟电路域。 连接到核心电源和数字电路模块的开关基于第二配置信号启用和禁用数字电路域。
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公开(公告)号：US20110128807A1
公开(公告)日：2011-06-02
申请号：US12697275
申请日：2010-01-31
申请人： Ashish Sharma , Lawrence F. Childs , Bikas Maiti , Manmohan Rana
发明人： Ashish Sharma , Lawrence F. Childs , Bikas Maiti , Manmohan Rana
摘要： A memory device includes a memory array, sense circuitry coupled to the memory array, and timing circuitry coupled to the sense circuitry. The timing circuitry generates a sense trigger signal to enable the sense circuitry. A strap region is formed adjacent the memory array. A reference word line is coupled to the timing circuitry. The reference word line formed in the strap region.
摘要翻译： 存储器件包括存储器阵列，耦合到存储器阵列的检测电路和耦合到感测电路的定时电路。 定时电路产生感测触发信号以使能感测电路。 带状区域形成在存储器阵列附近。 参考字线耦合到定时电路。 在带区域中形成的参考字线。
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公开(公告)号：US09286998B1
公开(公告)日：2016-03-15
申请号：US14525187
申请日：2014-10-27
申请人： Paramjeet Singh , Manmohan Rana
发明人： Paramjeet Singh , Manmohan Rana
CPC分类号： G11C17/16 , G11C11/5692 , G11C17/10 , G11C17/12 , G11C17/126 , H01L27/11226
摘要： A memory array includes multiple memory cells, multiple bit lines, multiple word lines, and multiple source lines. Each memory cell includes a corresponding transistor and stores first and second data values. The transistor has corresponding first and second bit lines, and a source line for retrieving the first and second data values. The transistor has a gate terminal connected to a corresponding word line for receiving a word line enable signal, a first diffusion terminal connected to ground, and a second diffusion terminal connected to at least one of the corresponding first bit line, second bit line, and the source line for determining the first and second data values. The second diffusion terminal may be floating for determining the first and second data values.
摘要翻译： 存储器阵列包括多个存储器单元，多个位线，多个字线和多个源极线。 每个存储单元包括相应的晶体管并存储第一和第二数据值。 晶体管具有对应的第一和第二位线，以及用于检索第一和第二数据值的源极线。 晶体管具有连接到对应字线的栅极端子，用于接收字线使能信号，连接到地的第一扩散端和连接到对应的第一位线，第二位线和 用于确定第一和第二数据值的源极线。 第二扩散终端可以是浮动的，用于确定第一和第二数据值。
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公开(公告)号：US09252751B2
公开(公告)日：2016-02-02
申请号：US14269194
申请日：2014-05-04
IPC分类号： H03K3/02 , H03K3/012 , G11C16/28 , G11C16/14 , G11C17/16 , G11C17/18 , H03K3/037 , H03K17/22
CPC分类号： H03K3/012 , G11C5/147 , G11C16/14 , G11C16/28 , G11C17/16 , G11C17/18 , G11C29/021 , G11C29/028 , G11C2029/0407 , H03K3/0375 , H03K17/22 , H03K17/223
摘要： Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
摘要翻译： 在引导期间，片上系统（SOC）中的多重复位可能会被避免，其中包括一系列在引导期间锁定修整值的锁存器，并保留 甚至在SOC复位事件期间的修整值。 SOC在引导期间或由于引导之外的任何原因退出复位时被阻止进入复位循环。 不依赖于任何调整值的上电复位比较器电路使锁存器能够自动清零锁存的微调值，如果其自身的电源电压低于预设电平。
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公开(公告)号：US20150378385A1
公开(公告)日：2015-12-31
申请号：US14318699
申请日：2014-06-30
IPC分类号： G05F3/16 , H03K3/038 , H03K3/3568 , H03K3/012
CPC分类号： G05F3/16 , H03K3/3562 , H03K19/0016
摘要： An integrated circuit that supports both internal and external voltage regulators as well as various modes, such as a low power mode or a test mode, includes voltage regulator selection circuitry and power control circuitry. The regulator selection circuitry selects one of internal and external regulators based on two pin conditions. The power control circuitry controls ON/OFF status of the regulators corresponding to a power mode, including power-on reset, entering a low power mode, and wake-up from a low power mode.
摘要翻译： 支持内部和外部稳压器以及各种模式（如低功耗模式或测试模式）的集成电路包括电压调节器选择电路和功率控制电路。 调节器选择电路根据两个引脚条件选择一个内部和外部稳压器。 功率控制电路控制与功率模式对应的稳压器的ON / OFF状态，包括上电复位，进入低功耗模式以及从低功耗模式唤醒。
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公开(公告)号：US20150318842A1
公开(公告)日：2015-11-05
申请号：US14269194
申请日：2014-05-04
CPC分类号： H03K3/012 , G11C5/147 , G11C16/14 , G11C16/28 , G11C17/16 , G11C17/18 , G11C29/021 , G11C29/028 , G11C2029/0407 , H03K3/0375 , H03K17/22 , H03K17/223
摘要： Multiple resets in a system-on-chip (SOC) during boot where on-board regulators and low voltage detector circuits have different trimmed and untrimmed values may be avoided by the inclusion of a series of latches that latch the trimmed values during boot and retain the trim values even during a SOC reset event. The SOC is prevented from entering into a reset loop during boot or when exiting reset for any reason other than boot. A power-on-reset comparator circuit that does not depend on any trim values enables the latches and only clears the latched trim values if its own supply voltage falls below a preset level.
摘要翻译： 在引导期间，片上系统（SOC）中的多重复位可能会被避免，其中包括一系列在引导期间锁定修整值的锁存器，并保留 甚至在SOC复位事件期间的修整值。 SOC在引导期间或由于引导之外的任何原因退出复位时被阻止进入复位循环。 不依赖于任何调整值的上电复位比较器电路使锁存器能够自动清零锁存的微调值，如果其自身的电源电压低于预设电平。
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公开(公告)号：US20140197883A1
公开(公告)日：2014-07-17
申请号：US13743324
申请日：2013-01-16
IPC分类号： G05F3/02
摘要： A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.
摘要翻译： 用于集成电路（IC）的阱偏置电路包括用于向阱偏压触点（n阱和p阱偏压触点）提供良好偏置电压（n阱和p阱偏置电压）的阱偏压调节器 ）当集成电路处于STOP和STANDBY模式时，IC的每个单元格。 在IC处于RUN和STOP模式和STANDBY模式时，开关连接在核心电源和阱偏压触点之间，用于连接和断开芯电源和阱偏压触点。 分别在IC处于RUN模式和STOP和STANDBY模式时，电压反相器电路和CMOS反相电路使能和禁止开关。
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公开(公告)号：US20090316464A1
公开(公告)日：2009-12-24
申请号：US12488624
申请日：2009-06-22
申请人： Ashish Sharma , Sanjeev Kumar Jain , Manmohan Rana
发明人： Ashish Sharma , Sanjeev Kumar Jain , Manmohan Rana
摘要： A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.
摘要翻译： ROM包括ROM阵列，地址解码器，控制电路，预充电跟踪器，预充电电路，参考字线，参考位线和参考检测发生器。 控制电路产生用于读取ROM的控制信号。 地址解码器支持位线和字线。 预充电跟踪器产生可编程预充电信号，该预充电信号被提供给预充电电路，用于预充电使能的位线。 基于可编程预充电信号和用于跟踪使能字线的控制信号使能参考字线。 基于用于跟踪使能的位线的参考字线使能参考位线。 参考检测发生器基于参考位线，可编程预充电信号和用于读取对应于使能位线和字线的位单元的控制信号产生可编程感测信号。
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