公开(公告)号：US20090234936A1

公开(公告)日：2009-09-17

申请号：US12048624

申请日：2008-03-14

Applicant: Justin Potok Bandholz ,  Clifton Ehrich Kerr ,  Pravin Patel ,  Bruce James Wilkie

Inventor： Justin Potok Bandholz ,  Clifton Ehrich Kerr ,  Pravin Patel ,  Bruce James Wilkie

IPC: G06F15/177

CPC classification number: G06F13/4072 ,  H04L12/40032 ,  H05K7/1492

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract translation: 在一个实施例中，用于多刀片服务器系统的通信系统包括将管理模块与多服务器机箱中的多个服务器中的每一个互连的多点串行总线网络。 第一收发器子系统被配置用于通过串行总线网络在管理模块和第一频带内的每个服务器之间进行通信。 第二收发器子系统被配置为在高于第一频带的第二频带内在管理模块和服务器之间通过串行总线网络同时通信。 第一信号滤波子系统基本上从第一收发器子系统滤出第二频带中的信号。 第二信号滤波子系统基本上从第二收发器子系统滤除第一频带中的信号。

公开(公告)号：US07525319B1

公开(公告)日：2009-04-28

申请号：US12200208

申请日：2008-08-28

Applicant: Rubina Firdaus Ahmed ,  Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Peter Robert Seidel

Inventor： Rubina Firdaus Ahmed ,  Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Peter Robert Seidel

IPC: G01R31/04 ,  G01R31/02 ,  G01R31/28

CPC classification number: G01R31/046

Abstract: A method of electrically qualifying high speed printed circuit board (PCB) connectors includes mounting a PCB connector on a test card, sending bit patterns through a first portion of the test card, evaluating a waveform on a sense signal on a second portion of the test card for the bit patterns launched on said first portion of the test card to measure common mode noise, and comparing the measured common mode noise of the second portion of the test card to a golden standard performed on a pre-qualified connector. The first portion of the test card comprises connectors to inject bit patterns. The second portion of the test card includes a split plane which induces common mode noise on a sense signal, the sense signal, and a termination pack. If the measured common mode noise on the PCB connector is worse than the golden standard, then the PCB connector is disqualified. If the measured common mode noise on the PCB connector is as good as or better than the golden standard, then the PCB connector is qualified. A first section of the PCB connector connects to the first portion of the test card and a second section of the PCB connector connects to the second portion of the test card. Transmission lines in the test card and the sense line are tightly coupled by shortening a distance between the sense line and the transmission lines.

Abstract translation: 电气限定高速印刷电路板（PCB）连接器的方法包括将PCB连接器安装在测试卡上，通过测试卡的第一部分发送位模式，在测试的第二部分上评估感测信号上的波形 在测试卡的所述第一部分上发射的位模式的卡用于测量共模噪声，以及将测试卡的第二部分的测量的共模噪声与在预先标定的连接器上执行的黄金标准进行比较。 测试卡的第一部分包括用于注入位模式的连接器。 测试卡的第二部分包括在感测信号，感测信号和终端包上引起共模噪声的分离平面。 如果PCB连接器上测得的共模噪声比黄金标准差，则PCB连接器不合格。 如果PCB连接器上测得的共模噪声与黄金标准一样好或更好，则PCB连接器是合格的。 PCB连接器的第一部分连接到测试卡的第一部分，并且PCB连接器的第二部分连接到测试卡的第二部分。 通过缩短感测线和传输线之间的距离，测试卡和感测线中的传输线紧密耦合。

公开(公告)号：US20090102487A1

公开(公告)日：2009-04-23

申请号：US11875001

申请日：2007-10-19

Applicant: Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Celeb James Wesley

Inventor： Moises Cases ,  Bradley Donald Herrman ,  Kent Barclay Howieson ,  Erdem Matoglu ,  Bhyrav Murthy Mutnury ,  Pravin Patel ,  Nam Huu Pham ,  Celeb James Wesley

IPC: G01R31/02 ,  G01K3/00 ,  G01N25/72

CPC classification number: G01N25/72 ,  G01J5/0096 ,  G01R31/2818 ,  G01R31/2837 ,  G01R31/309

Abstract: A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.

Abstract translation: 一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。 当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。 测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。 尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

公开(公告)号：US20090021264A1

公开(公告)日：2009-01-22

申请号：US11780505

申请日：2007-07-20

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G01R31/02 ,  G06F11/00

CPC classification number: G01R31/2815 ,  G01R31/304 ,  G11C29/02 ,  G11C29/022 ,  G11C29/56 ,  G11C2029/5602

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract translation: 本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。 辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。 辐射功率与驱动位的频率成正比。 通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点 ，例如通过探测DIMM的触点。

公开(公告)号：US20090007048A1

公开(公告)日：2009-01-01

申请号：US12203335

申请日：2008-09-03

Applicant: MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

Inventor： MOISES CASES ,  Martin J. Crippen ,  Daniel N. de Araujo ,  Bradley D. Herman ,  Erdem Matoglu ,  William R. Milani ,  Bhyrav M. Mutnury ,  Pravin Patel ,  Nam H. Pham

IPC: G06F17/50

CPC classification number: H01R25/006

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory module system and DIMM connector is provided. A DIMM connector includes a plurality of DIMM sockets for receiving a corresponding plurality of DIMMs in a radially oriented, angularly spaced orientation. The DIMM sockets are connected in parallel at a memory module junction so that socket terminals of each DIMM socket are joined to the same relative terminal of all the other DIMM sockets along electronic pathways of substantially equal length. A memory controller selectively communicates with the DIMMs via the DIMM junction. By virtue of the improved topology, impedance within the DIMM connector may be better matched to minimize reflections and improve signal quality.

Abstract translation: 提供了体现在用于设计，制造和/或测试存储器模块系统和DIMM连接器的机器可读存储介质中的设计结构。 DIMM连接器包括多个DIMM插座，用于以径向定向的，有角度间隔的方向接收相应的多个DIMM。 DIMM插槽在存储器模块连接处并联连接，使得每个DIMM插座的插座端子沿着基本相等长度的电子路径连接到所有其他DIMM插槽的相同相对端子。 存储器控制器经由DIMM连接器选择性地与DIMM通信。 凭借改进的拓扑结构，可以更好地匹配DIMM连接器内的阻抗以最小化反射并提高信号质量。

公开(公告)号：US20080278207A1

公开(公告)日：2008-11-13

申请号：US11746102

申请日：2007-05-09

Applicant: Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

Inventor： Henry G. McMillan ,  Pravin Patel ,  Challis L. Purrington ,  Gwendolyn R. Tobin ,  Christopher C. West ,  Ivan R. Zapata

IPC: H03K5/12

CPC classification number: H03K5/1534 ,  H03K19/01721

Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

Abstract translation: 本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。 在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。 下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。 电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。 最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

公开(公告)号：US20080188095A1

公开(公告)日：2008-08-07

申请号：US11670015

申请日：2007-02-01

Applicant: Robert Joseph Christopher ,  Pravin Patel ,  Tony Carl Sass

Inventor： Robert Joseph Christopher ,  Pravin Patel ,  Tony Carl Sass

IPC: H01R12/00

CPC classification number: H01R13/6477 ,  H01R13/6471 ,  H01R13/6474 ,  H05K1/024

Abstract: Connector and methods of connector design and manufacture are disclosed for achieving a desired phase relationship between signals carried along conductors of different lengths, while maintaining a desired impedance of the conductors. In one embodiment, a PCB connector includes a first plurality of electronic terminals and a second plurality of electronic terminals disposed on a connector body. A substrate has a dielectric constant that varies with location within the substrate. A first electronic conductor follows a first pathway within the substrate to experience a first effective dielectric constant. A second electronic conductor follows a second pathway within the substrate to experience a second effective dielectric constant. The first electronic conductor is longer than the second electronic conductor and the first effective dielectric constant is less than the second effective dielectric constant, to at least reduce phase error between signals. By satisfying the relationship l1/l2=sqrt(ε2/ε1), a phase error may be avoided.

Abstract translation: 公开连接器和连接器设计和制造的方法，用于在保持导体的期望阻抗的同时实现沿着不同长度的导体携带的信号之间的期望的相位关系。 在一个实施例中，PCB连接器包括第一多个电子端子和设置在连接器主体上的第二多个电子端子。 衬底具有随着衬底内的位置而变化的介电常数。 第一电子导体遵循衬底内的第一路径以经历第一有效介电常数。 第二电子导体遵循衬底内的第二路径以经历第二有效介电常数。 第一电子导体比第二电子导体长，并且第一有效介电常数小于第二有效介电常数，以至少减小信号之间的相位误差。 通过满足关系l 1/2/2 / sqrt（ε2 /ε1 1），相位误差 可以避免。

公开(公告)号：US08873249B2

公开(公告)日：2014-10-28

申请号：US13439221

申请日：2012-04-04

Applicant: Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

Inventor： Justin P. Bandholz ,  Brian M. Kerrigan ,  Edward J. McNulty ,  Pravin Patel ,  Peter R. Seidel ,  Philip L. Weinstein

IPC: H05K1/11 ,  G06F1/18

CPC classification number: G06F1/185 ,  Y10T29/49147

Abstract: A DIMM riser card that includes a PCB having a first edge, a second edge, and one or more faces. The first edge of the PCB is configured for insertion into a main board DIMM socket. The first edge includes electrical traces that electrically couple to a memory bus. The DIMM riser card includes an angled DIMM socket mounted on one face of the PCB, where the angled DIMM socket is configured to accept a DIMM at an angle not perpendicular to the PCB and electrically couple the DIMM to the memory bus. The DIMM riser card includes a straddle mount DIMM socket mounted on the second edge of the PCB. The straddle mount DIMM socket is configured to accept a DIMM and electrically couple the DIMM to the memory bus through the electrical traces on the first edge of the PCB.

Abstract translation: 一种DIMM转接卡，其包括具有第一边缘，第二边缘和一个或多个面部的PCB。 PCB的第一个边缘被配置为插入主板DIMM插槽。 第一个边缘包括电耦合到存储器总线的电迹线。 DIMM转接卡包括安装在PCB的一个面上的倾斜的DIMM插槽，其中倾斜的DIMM插槽被配置为以不垂直于PCB的角度接受DIMM并将DIMM电耦合到存储器总线。 DIMM转接卡包括安装在PCB第二边缘上的跨骑式DIMM插槽。 跨骑式DIMM插槽被配置为接受DIMM并通过PCB第一边缘上的电迹线将DIMM电连接到存储器总线。

公开(公告)号：US20140102529A1

公开(公告)日：2014-04-17

申请号：US13741070

申请日：2013-01-14

Applicant: Cory Tourino ,  Arthur Cornfeld ,  Pravin Patel ,  Andreea Boca

Inventor： Cory Tourino ,  Arthur Cornfeld ,  Pravin Patel ,  Andreea Boca

IPC: H01L31/02

CPC classification number: H01L31/02008 ,  H01L31/0512 ,  Y02E10/50

Abstract: A solar cell interconnect assembly and a method for manufacturing the same are provided. In an embodiment, the method may include: providing a solar cell having an interconnect member formed thereon, the interconnect member comprising a metallic part formed on a surface of the solar cell and a first precursor layer formed over the metallic part; providing an interconnector comprising a second precursor layer at a surface thereof; heating the interconnector and the interconnect member to a temperature equal to or above a eutectic temperature of the materials of the first and second precursor layers and pressing one of them against the other so as to form a eutectic liquid phase; and isothermal solidifying the eutectic liquid to form a bonding layer of eutectic alloy.

Abstract translation: 提供了一种太阳能电池互连组件及其制造方法。 在一个实施例中，该方法可以包括：提供具有形成在其上的互连构件的太阳能电池，所述互连构件包括形成在太阳能电池的表面上的金属部分和形成在金属部分上的第一前体层; 提供在其表面上包括第二前体层的互连器; 将互连器和互连构件加热到等于或高于第一和第二前体层的材料的共晶温度的温度，并将它们中的一个压在另一个之上以形成共晶液相; 等温固化共晶液体，形成共晶合金的粘结层。

公开(公告)号：US20140032436A1

公开(公告)日：2014-01-30

申请号：US13897464

申请日：2013-05-20

Applicant: DHRUV PRAVIN PATEL

Inventor： DHRUV PRAVIN PATEL

IPC: G06Q10/10

CPC classification number: G06Q10/1053

Abstract: The present invention in a preferred embodiment provides systems and methods for facilitation of recruitment or hiring on an online interface which provide the employer with the “jobseekers' search list” based on a predefined questionnaire or custom questionnaire comprising of direct questions or queries or multiple choice options, whereby any descriptive or elaborate answers or details are eliminated. Jobseekers' attributes are matched with employers' desired job attributes based on the predefined questionnaire or custom questionnaires. Matching of the attributes generates scores or ranks depending on a pre-defined system and weightage provided to specific job attributes.

Abstract translation: 在优选实施例中的本发明提供了用于在在线界面上促进招聘或招聘的系统和方法，其基于包括直接问题或查询或多重选择的预定问卷或定制问卷向雇主提供“求职者搜索列表” 选项，从而消除任何描述性或精心设计的答案或细节。 基于预定义的问卷或自定义问卷调查，求职者的属性与雇主的期望工作属性相匹配。 属性的匹配根据预定义的系统和提供给特定作业属性的权重生成分数或等级。