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    Method of manufacturing a transistor
    13.
    发明申请
    Method of manufacturing a transistor 失效
    制造晶体管的方法

    公开(公告)号：US20050048729A1

    公开(公告)日：2005-03-03

    申请号：US10898484

    申请日：2004-07-22

    Applicant: Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    Inventor： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

    IPC: H01L21/334 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

    Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

    Abstract translation: 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

    Methods of forming and operating field effect transistors having gate and sub-gate electrodes
    14.
    发明授权
    Methods of forming and operating field effect transistors having gate and sub-gate electrodes 有权
    形成和操作具有栅极和子栅电极的场效应晶体管的方法

    公开(公告)号：US06680224B2

    公开(公告)日：2004-01-20

    申请号：US10389846

    申请日：2003-03-17

    Applicant: Hyung-cheol Shin ,  Jong-ho Lee ,  Sang-yeon Han

    Inventor： Hyung-cheol Shin ,  Jong-ho Lee ,  Sang-yeon Han

    IPC: H01L218234

    CPC classification number: H01L29/66643 ,  H01L21/2807 ,  H01L21/28105 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/7831 ,  H01L29/7836

    Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.

    Abstract translation: 场效应晶体管包括其中具有第一导电类型的沟道区的半导体衬底，其在其表面附近延伸。 第二导电类型的源极和漏极区域也设置在沟道区域的相对端。 源区和漏区在半导体衬底中延伸并与沟道区形成P-N整流结。 栅电极在沟道区域上延伸并且包括具有第一功函数的第一导电材料。 第一子栅极电极在沟道区域上延伸并且包括具有不等于第一功函数的第二功函数的第二导电材料。 优选选择第二导电材料，使得第二功函数和沟道区的功函数之间的差足以在沟道区域的与第一子栅电极相对延伸的部分中形成反转层，当第 第一子栅极电极相对于沟道区域处于零电位偏置。

    Gate electrode and gate contact plug layouts for integrated circuit field effect transistors
    15.
    发明授权
    Gate electrode and gate contact plug layouts for integrated circuit field effect transistors 有权
    用于集成电路场效应晶体管的栅电极和栅极接触插头布局

    公开(公告)号：US09418988B2

    公开(公告)日：2016-08-16

    申请号：US14461202

    申请日：2014-08-15

    Applicant: Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

    Inventor： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

    IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

    Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

    Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

    Semiconductor device including a fin field effect transistor and method of manufacturing the same
    17.
    发明授权
    Semiconductor device including a fin field effect transistor and method of manufacturing the same 有权
    包括鳍状场效应晶体管的半导体器件及其制造方法

    公开(公告)号：US07936021B2

    公开(公告)日：2011-05-03

    申请号：US11976252

    申请日：2007-10-23

    Applicant: Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

    Inventor： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

    IPC: H01L29/78 ,  H01L21/336 ,  H01L27/108

    CPC classification number: H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

    Abstract: In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

    Abstract translation: 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

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