公开(公告)号：US07795678B2

公开(公告)日：2010-09-14

申请号：US12137573

申请日：2008-06-12

Applicant: Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

Inventor： Jong-Man Park ,  Satoru Yanada ,  Sang-Yeon Han ,  Jun-Bum Lee ,  Si-Ok Sohn

IPC: H01L29/739

CPC classification number: H01L21/76232 ,  H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate.

Abstract translation: 半导体器件包括在其上形成晶体管的有源图案和衬底之间的掩埋隔离图案。 有源图案具有各自沿第一方向纵向延伸的相邻部分。 场隔离图案插入在活动图案的相邻部分之间。 埋置隔离图案具有在活动图案的每个部分下沿第一方向彼此间隔开的部分。 掩埋隔离图案的每个部分在垂直于第一方向的第二方向上从场隔离图案的下部延伸。 至少一个栅极结构设置在有源图案的每个部分上，并且杂质区域位于活性图案的上表面处的栅极结构附近。 杂质区域与第一和第二方向垂直的第三方向与掩埋隔离图案间隔开。 掩埋隔离图案提供了由施加到基底的偏压引起的身体效应的控制。

公开(公告)号：US20080308863A1

公开(公告)日：2008-12-18

申请号：US12137573

申请日：2008-06-12

Applicant: Jong-Man PARK ,  Satoru YANADA ,  Sang-Yeon HAN ,  Jun-Bum LEE ,  Si-Ok SOHN

Inventor： Jong-Man PARK ,  Satoru YANADA ,  Sang-Yeon HAN ,  Jun-Bum LEE ,  Si-Ok SOHN

IPC: H01L29/739 ,  H01L21/336

CPC classification number: H01L21/76232 ,  H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions. The buried isolation pattern offers a control on the body effect caused by a bias applied to the substrate.

Abstract translation: 半导体器件包括在其上形成晶体管的有源图案和衬底之间的掩埋隔离图案。 有源图案具有各自沿第一方向纵向延伸的相邻部分。 场隔离图案插入在活动图案的相邻部分之间。 埋置隔离图案具有在活动图案的每个部分下沿第一方向彼此间隔开的部分。 掩埋隔离图案的每个部分在垂直于第一方向的第二方向上从场隔离图案的下部延伸。 至少一个栅极结构设置在有源图案的每个部分上，并且杂质区域位于活性图案的上表面处的栅极结构附近。 杂质区域与第一和第二方向垂直的第三方向与掩埋隔离图案间隔开。 掩埋隔离图案提供了由施加到基底的偏压引起的身体效应的控制。

公开(公告)号：US20080099850A1

公开(公告)日：2008-05-01

申请号：US11976252

申请日：2007-10-23

Applicant: Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

Inventor： Chang-Hoon Jeon ,  Satoru Yamada ,  Sang-Yeon Han ,  Jong-Man Park ,  Si-Ok Sohn

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: In a fin field effect transistor (Fin FET)and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening exposing a sidewall of the active pattern located between the insulating layer patterns is formed, a gate electrode formed on the active pattern to fill the opening, impurity regions formed at portions of the active pattern adjacent to sidewalls of the gate electrode, an insulating interlayer covering the active pattern and the gate electrode and contact plugs formed through portions of the insulating interlayer and the active pattern adjacent to the sidewalls of the gate electrode such that the contact plug makes contact with the impurity region.

Abstract translation: 在翅片场效应晶体管（Fin FET）和制造Fin FET的方法中，Fin FET包括其中形成绝缘层图案的有源图案，包围有源图案的侧壁的隔离层图案，使得开口露出 形成位于绝缘层图案之间的有源图案的侧壁，形成在有源图案上以填充开口的栅电极，形成在与栅电极的侧壁相邻的有源图案的部分处的杂质区，覆盖 有源图案和通过绝缘夹层的一部分和与栅电极的侧壁相邻的有源图案形成的栅电极和接触插塞，使得接触插塞与杂质区接触。

公开(公告)号：US07265011B2

公开(公告)日：2007-09-04

申请号：US10898484

申请日：2004-07-22

Applicant: Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

Inventor： Jae-Man Yoon ,  Dong-gun Park ,  Makoto Yoshida ,  Gyo-Young Jin ,  Jeong-dong Choe ,  Sang-Yeon Han

IPC: H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/66537

Abstract: A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

Abstract translation: 根据一些实施例的制造晶体管的方法包括在半导体衬底的有源区上依次形成伪栅极氧化物层和虚拟栅电极，将第一导电杂质离子注入到源/漏区中以形成第一杂质区， 并离子注入第一导电杂质以形成与第一杂质区重叠的第二杂质区。 该方法包括在源极/漏极区域上形成焊盘多晶硅层，从半导体衬底的栅极区域顺序地去除焊盘多晶硅层和伪栅电极，退火半导体衬底，并离子注入第二导电杂质以形成 栅极区域中的第三杂质区域。 该方法包括去除伪栅极氧化物层，形成栅极绝缘层，以及在栅极区域上形成栅电极。

公开(公告)号：US20070085127A1

公开(公告)日：2007-04-19

申请号：US11637793

申请日：2006-12-13

Applicant: Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

Inventor： Hee-Soo Kang ,  Jae-Man Yoon ,  Dong-Gun Park ,  Sang-Yeon Han ,  Young-Joon Ahn ,  Choong-Ho Lee

IPC: H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC classification number: H01L29/7851 ,  H01L29/66818 ,  Y10S257/90

Abstract: A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.

Abstract translation: 公开了一种翅片式MOSFET及其制造方法。 鳍型MOSFET中的栅极结构通过未经光刻工艺的镶嵌工艺形成。 用于形成沟道区域的杂质被选择性地注入到与栅极结构相邻的半导体衬底的部分中。

公开(公告)号：US06563151B1

公开(公告)日：2003-05-13

申请号：US09654859

申请日：2000-09-05

Applicant: Hyung-cheol Shin ,  Jong-ho Lee ,  Sang-yeon Han

Inventor： Hyung-cheol Shin ,  Jong-ho Lee ,  Sang-yeon Han

IPC: H01L2976

CPC classification number: H01L29/66643 ,  H01L21/2807 ,  H01L21/28105 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/7831 ,  H01L29/7836

Abstract: Field effect transistors include a semiconductor substrate having a channel region of first conductivity type therein extending adjacent a surface thereof. Source and drain regions of second conductivity type are also provided at opposite ends of the channel region. The source and drain regions extend in the semiconductor substrate and form P-N rectifying junctions with the channel region. A gate electrode extends on the channel region and comprises a first electrically conductive material having a first work function. A first sub-gate electrode extends on the channel region and comprises a second electrically conductive material having a second work function that is unequal to the first work function. The second electrically conductive material is preferably selected so that a difference between the second work function and a work function of the channel region is sufficient to form an inversion-layer in a portion of the channel region extending opposite the first sub-gate electrode when the first sub-gate electrode is at a zero potential bias relative to the channel region.

公开(公告)号：US07358142B2

公开(公告)日：2008-04-15

申请号：US11046623

申请日：2005-01-28

Applicant: Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

Inventor： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

Abstract translation: 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源区和漏区形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

公开(公告)号：US20050170593A1

公开(公告)日：2005-08-04

申请号：US11046623

申请日：2005-01-28

Applicant: Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

Inventor： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8228 ,  H01L29/786 ,  H01M8/00

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

Abstract translation: 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源极和漏极区域形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

公开(公告)号：US08823113B2

公开(公告)日：2014-09-02

申请号：US12984762

申请日：2011-01-05

Applicant: Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

Inventor： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。

公开(公告)号：US20120001271A1

公开(公告)日：2012-01-05

申请号：US12984762

申请日：2011-01-05

Applicant: Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

Inventor： Kyo-Suk Chae ,  Satoru Yamada ,  Sang-Yeon Han ,  Young-Jin Choi ,  Wook-Je Kim

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/7833

Abstract: A four transistor layout can include an isolation region that defines an active region, the active region extending along first and second different directions. A common source region of the four transistors extends from a center of the active region along both the first and second directions to define four quadrants of the active region that are outside the common source region. Four drain regions are provided, a respective one of which is in a respective one of the four quadrants and spaced apart from the common source region. Finally, four gate electrodes are provided, a respective one of which is in a respective one of the four quadrants between the common source region and a respective one of the four drain regions. A respective gate electrode includes a vertex and first and second extending portions, the first extending portions extending from the vertex along the first direction and the second extending portions extending from the vertex along the second direction.

Abstract translation: 四晶体管布局可以包括限定有源区域的隔离区域，有源区域沿第一和第二不同方向延伸。 四个晶体管的共同源极区域从有源区域的中心沿着第一和第二方向延伸，以限定位于公共源极区域外的有源区域的四个象限。 设置四个漏极区，其中的一个位于四个象限中的相应一个中并与公共源极区间隔开。 最后，提供四个栅电极，其中的一个位于公共源极区域和四个漏极区域中的相应一个之间的四个象限中的相应一个中。 相应的栅电极包括顶点和第一和第二延伸部分，第一延伸部分从顶点沿着第一方向延伸，第二延伸部分从顶点沿着第二方向延伸。