公开(公告)号：US20150381442A1

公开(公告)日：2015-12-31

申请号：US14317288

申请日：2014-06-27

Applicant: Brian Delgado ,  Brian S. Payne ,  Barry E. Huntley ,  Scott D. Rodgers

Inventor： Brian Delgado ,  Brian S. Payne ,  Barry E. Huntley ,  Scott D. Rodgers

IPC: H04L12/26 ,  G06F9/455 ,  H04L29/06

CPC classification number: H04L43/065 ,  G06F9/45558 ,  G06F2009/45591 ,  H04L63/0807

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a system management monitor to receive a platform query request from an external system, obtain status information regarding a configuration of one or more privileged resources of the processor, and report the status information to the external system. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核心和用于从外部系统接收平台查询请求的系统管理监视器，获得关于处理器的一个或多个特权资源的配置的状态信息，并且报告状态 信息给外部系统。 描述和要求保护其他实施例。

公开(公告)号：US20130246824A1

公开(公告)日：2013-09-19

申请号：US13891747

申请日：2013-05-10

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。

公开(公告)号：US20130219143A1

公开(公告)日：2013-08-22

申请号：US13837822

申请日：2013-03-15

Applicant: Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC: G06F12/14

CPC classification number: G06F12/1483 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/657

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

公开(公告)号：US20110154079A1

公开(公告)日：2011-06-23

申请号：US12641534

申请日：2009-12-18

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  Taraneh Bahrami ,  Stephen H. Gunther ,  Prashant Sethi ,  Per Hammarlund

IPC: G06F1/32 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3293 ,  G06F9/30083 ,  G06F9/3009 ,  Y02D10/122 ,  Y02D50/20

Abstract: In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有解码逻辑的核的处理器，用于解码指定要监视的位置的标识的指令和定时器值，以及耦合到解码逻辑的定时器，以执行相对于 定时器值。 处理器还可以包括耦合到核的功率管理单元，以至少部分地基于定时器值来确定低功率状态的类型，并且使处理器响应于该确定而进入低功率状态。 描述和要求保护其他实施例。

公开(公告)号：US20080091917A1

公开(公告)日：2008-04-17

申请号：US11546710

申请日：2006-10-11

Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

IPC: G06F15/76

CPC classification number: G06F21/79 ,  G06F12/1441 ,  G06F2221/2141

Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

Abstract translation: 在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。 系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求 如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

公开(公告)号：US5636374A

公开(公告)日：1997-06-03

申请号：US470842

申请日：1995-06-06

Applicant: Scott D. Rodgers ,  Keshavan K. Tiruvallur ,  Michael W. Rhodehamel ,  Kris G. Konigsfeld ,  Andrew F. Glew ,  Haitham Akkary ,  Milind A. Karnik ,  James A. Brayton

Inventor： Scott D. Rodgers ,  Keshavan K. Tiruvallur ,  Michael W. Rhodehamel ,  Kris G. Konigsfeld ,  Andrew F. Glew ,  Haitham Akkary ,  Milind A. Karnik ,  James A. Brayton

IPC: G06F9/312 ,  G06F12/08 ,  G06F12/10 ,  G06F9/30

CPC classification number: G06F9/30043 ,  G06F12/0891 ,  G06F12/1027

Abstract: In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.

Abstract translation: 在微处理器中，用于执行存储器功能并发布总线周期的装置和方法。 特殊的微指令存储在微码ROM中。 这些微指令用于执行存储器功能并产生特殊的总线周期。 最初，对于这些特殊微指令之一产生与要执行的请求操作相对应的地址。 该特殊微指令及其地址然后通过总线传输到微处理器的各个单元。 当每个单元接收微指令时，它根据该地址确定该微指令是否被忽略。 如果特定单元忽略微指令，则微指令将转发到管道中的后续单元进行处理。 否则，如果该特定单元执行由微指令的地址指定的请求操作。

公开(公告)号：US20150007304A1

公开(公告)日：2015-01-01

申请号：US13930766

申请日：2013-06-28

Applicant: Lior Malka ,  Koichi Yamada ,  Palanivelrajan Shanmugavelayutham ,  Barry E. Huntley ,  Scott D. Rodgers ,  James D. Beaney, JR.

Inventor： Lior Malka ,  Koichi Yamada ,  Palanivelrajan Shanmugavelayutham ,  Barry E. Huntley ,  Scott D. Rodgers ,  James D. Beaney, JR.

IPC: G06F21/52

CPC classification number: G06F21/74 ,  G06F21/54

Abstract: A processor and method are described for managing different privilege levels associated with different types of program code, including binary translation program code. For example, one embodiment of a method comprises entering into one of a plurality of privilege modes responsive to detecting the execution of a corresponding one of a plurality of different types of program code including native executable program code, translated executable program code, and binary translation program code. In one embodiment, the binary translation program code includes sub-components each of which are associated with a different privilege level for improved security.

Abstract translation: 描述了处理器和方法，用于管理与不同类型的程序代码相关联的不同特权级别，包括二进制翻译程序代码。 例如，方法的一个实施例包括响应于检测到多个不同类型的程序代码中的相应的一个程序代码的执行，包括本机可执行程序代码，翻译的可执行程序代码和二进制转换，来进入多个特权模式之一 程序代码。 在一个实施例中，二进制翻译程序代码包括子组件，每个子组件与不同的权限级别相关联，以提高安全性。

公开(公告)号：US20120173852A1

公开(公告)日：2012-07-05

申请号：US13417241

申请日：2012-03-10

Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

公开(公告)号：US07966476B2

公开(公告)日：2011-06-21

申请号：US12039719

申请日：2008-02-28

Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

公开(公告)号：US20080148019A1

公开(公告)日：2008-06-19

申请号：US12039719

申请日：2008-02-28

Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。